MCF5272 Datasheet, PDF (148/544 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

Debug Support
5.5.3.3.8 No Operation (NOP)
NOP performs no operation and may be used as a null command where required.
Command Formats:
15
12
11
8
7
4
3
0
0x0
0x0
0x0
0x0
Figure 5-31. NOP Command Format
Command Sequence:
Operand Data:
Result Data:
NOP
NEXT CMD
???
"CMD COMPLETE"
Figure 5-32. NOP Command Sequence
None
The command-complete response, 0xFFFF (with S cleared), is returned during the
next shift operation.
5.5.3.3.9 Read Control Register (RCREG)
Read the selected control register and return the 32-bit result. Accesses to the processor/memory control
registers are always 32 bits wide, regardless of register width. The second and third words of the command
form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified
control register. The 12-bit Rc field is the same as that used by the MOVEC instruction.
Command/Result Formats:
15
12 11
8
7
4
3
0
Command
0x2
0x9
0x8
0x0
0x0
0x0
0x0
0x0
0x0
Result
Rc
D[31:16]
D[15:0]
Figure 5-33. RCREG Command/Result Formats
Rc encoding:
Table 5-19. Control Register Map
Rc
Register Definition
0x002 Cache control register (CACR)
0x004 Access control register 0 (ACR0)
0x005 Access control register 1 (ACR1)
0x801 Vector base register (VBR)
0x804 MAC status register (MACSR)
0x805 MAC mask register (MASK)
Rc
Register Definition
0x806 MAC accumulator (ACC)
0x80E Status register (SR)
0x80F Program register (PC)
0xC04 RAM base address register (RAMBAR)
0xC0F Module base address (MBAR)
5-30
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor