MCF5272 Datasheet, PDF (327/544 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

Physical Layer Interface Controller (PLIC)
13.5.19 D-Channel Status Register (PDCSR)
All bits in this register are read only and are cleared on hardware or software reset. The register is also
cleared after a read operation.
The PDCSR register contains the D-channel status bits for all four ports on the MCF5272.
Field
7
6
—
5
DG1
4
DG0
3
DC3
2
DC2
1
DC1
0
DC0
Reset
0000_0000
R/W
Read Only
Addr
MBAR + 0x383
Figure 13-31. D-Channel Status Register (PDCSR)
Table 13-14. PDCSR Field Descriptions
Bits
Name
Description
7–6
— Reserved, should be cleared.
5
DG1 D-channel grant, port 1.
0 Default reset value.
1 In IDL mode, indicates the status of DGRANT. When the external DGNT has a logic 1, the
corresponding DG1/DG0 bit is set. In GCI mode, DG1 and DG0 reflects the inverted value of the
SCIT bit. The significance of this bit is the same in IDL or GCI mode, that is, in IDL mode when the
DG bit is set, the D channel is granted. In GCI mode when the DG bit is set, this corresponds to the
GO condition. In both cases the D channel is granted and communication may commence.
4
DG0 D-channel grant, port 0. See DG1.
3
DC3 D-channel change, port 3.
0 Default reset value.
1 Indicates that a value other than 0xFF (all ones) exists the D-channel receive register.
2
DC2 D-channel change, port 2. See DC3.
1
DC1 D-channel change, port 1. See DC3.
0
DC0 D-channel change, port 0. See DC3.
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-31