MCF5272 Datasheet, PDF (230/544 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

Ethernet Module
11.5.2 Interrupt Event Register (EIR)
An event that sets a bit in EIR generates an interrupt if the corresponding bit in the interrupt mask register
(EIMR) is set. Bits in the interrupt event register are cleared when a one is written to them. Writing a zero
has no effect.
31
30
29
28
27
26
25
24 23
22
21
20
16
Field HBERR BABR BABT GRA TXF TXB RXF RXB MII EBERR UMINT
—
Reset
0000_0000_0000_0000
R/W
Read/write
15
0
Field
—
Reset
0000_0000_0000_0000
R/W
Read/write
Addr
MBAR + 0x844
Figure 11-6. Interrupt Event Register (EIR)
Bits
31
30
29
28
27
26
25
24
23
22
21
20–0
Table 11-8. EIR Field Descriptions
Name
Description
HBERR
BABR
BABT
GRA
TXF
TXB
RXF
RXB
MII
EBERR
UMINT
—
Heartbeat error. A heartbeat was not detected within the heartbeat window following a transmission.
Babbling receive error. A frame was received with length in excess of MAX_FL bytes.
Babbling transmit error. The transmitted frame length has exceeded MAX_FL bytes. This condition is
usually caused by a frame that is too long being placed into the transmit data buffer(s). Truncation does
not occur.
Graceful stop complete. A graceful stop, which was initiated by setting X_CTRL[GTS], is now complete.
This bit is set as soon as the transmitter has finished transmitting any frame that was in progress when
GTS was set.
Transmit frame interrupt. A frame has been transmitted and that the last corresponding buffer descriptor
has been updated.
Transmit buffer interrupt. A transmit buffer descriptor has been updated.
Receive frame interrupt. A frame has been received and the last corresponding buffer descriptor has
been updated.
Receive buffer interrupt. A receive buffer descriptor has been updated.
MII interrupt. The MII has completed the data transfer requested.
FEC bus error. A bus error occurred when the FEC was accessing an internal bus.
Unmasked interrupt status. An interrupt is currently being asserted to the interrupt controller. This bit is
not maskable.
Reserved, should be cleared.
11-12
MCF5272 ColdFire^® Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor