MC9S12XEP100MAG Datasheet, PDF (515/1324 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
Table 13-13. ATDCTL4 Field Descriptions
Field
Description
7–5
SMP[2:0]
4–0
PRS[4:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 13-14 lists the available sample time lengths.
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
fATDCLK = _2-----×-----₍--f-P-B---R-U----S-S----+-----1-----₎
Refer to Device Specification for allowed frequency range of f_ATDCLK.
SMP2
0
0
0
0
1
1
1
1
Table 13-14. Sample Time Select
SMP1
0
0
1
1
0
0
1
1
SMP0
0
1
0
1
0
1
0
1
Sample Time
in Number of
ATD Clock Cycles
4
6
8
10
12
16
20
24
13.3.2.6 ATD Control Register 5 (ATDCTL5)
Writes to this register will abort current conversion sequence and start a new conversion sequence. If
external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a
conversion sequence which will then occur on each trigger event. Start of conversion means the beginning
of the sampling phase.
Module Base + 0x0005
7
R
0
W
Reset
0
6
5
4
3
2
1
0
SC
SCAN
MULT
CD
CC
CB
CA
0
0
0
0
0
0
0
Figure 13-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime
Write: Anytime
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
515