MC9S12XEP100MAG Datasheet, PDF (252/1324 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-14. Read Access (n–1 Cycles)
DATA[15:0] (external read) ... ?
z
z
z
z
z ... data 0
RW
... 1
1
1
1
1
1 ... 1
z ...
1 ...
5.4.2.4.2 Write Access Timing
Table 5-15. Write Access (1 Cycle)
Access #0
Access #1
Access #2
Bus cycle ->
...
1
2
3
...
ECLK phase
... high
low
high
low
high
low ...
ADDR[22:20] / ACC[2:0] ...
acc 0
acc 1
acc 2 ...
ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat -1 addr 1 iqstat 0 addr 2 iqstat 1 ...
ADDR[15:0] / IVD[15:0] ...
?
x
x ...
DATA[15:0] (write)
... ?
data 0
data 1
data 2 ...
RW
... 0
0
1
1
1
1 ...
Table 5-16. Write Access (2 Cycles)
Access #0
Access #1
Bus cycle ->
...
1
2
3
...
ECLK phase
... high
low
high
low
high
low ...
ADDR[22:20] / ACC[2:0] ...
acc 0
000
acc 1 ...
ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat-1 addr 0 iqstat 0 addr 1 0000 ...
ADDR[15:0] / IVD[15:0] ...
?
x
x ...
DATA[15:0] (write)
... ?
data 0
x ...
RW
... 0
0
0
0
1
1 ...
Table 5-17. Write Access (n–1 Cycles)
Access #0
Access #1
Bus cycle ->
...
1
2
3
...
n
...
ECLK phase
... high
low
high
low
high
low ... high
low ...
ADDR[22:20] / ACC[2:0] ...
acc 0
000
000 ...
acc 1 ...
ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat-1 addr 0 iqstat 0 addr 0 0000 ... addr 1 0000 ...
ADDR[15:0] / IVD[15:0] ...
?
x
x ...
x ...
DATA[15:0] (write)
... ?
data 0
x ...
RW
... 0
0
0
0
0
0 ... 1
1 ...
5.4.2.4.3 Read-Write-Read Access Timing
Table 5-18. Interleaved Read-Write-Read Accesses (1 Cycle)
Bus cycle ->
Access #0
...
1
Access #1
2
Access #2
3
...
MC9S12XE-Family Reference Manual Rev. 1.25
252
Freescale Semiconductor