MC9S12XEP100MAG Datasheet, PDF (281/1324 Pages) Freescale Semiconductor, Inc – Reference Manual Covers MC9S12XE Family

Chapter 7 Background Debug Module (S12XBDMV2)
7.1.2.3 Low-Power Modes
The BDM can be used until all bus masters (e.g., CPU or XGATE or others depending on which masters
are available on the SOC) are in stop mode. When CPU is in a low power mode (wait or stop mode) all
BDM firmware commands as well as the hardware BACKGROUND command can not be used
respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and
write commands are available. Also the CPU can not enter a low power mode during BDM active mode.
If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled
and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft
reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM
is now ready to receive a new command.
7.1.3 Block Diagram
A block diagram of the BDM is shown in Figure 7-1.
Host
System _BKGD
Serial
Interface
Register Block
Data
Control
16-Bit Shift Register
TRACE
BDMACT
Instruction Code
and
Execution
Bus Interface
and
Control Logic
Address
Data
Control
Clocks
ENBDM
SDV
UNSEC
CLKSW
BDMSTS
Register
Standard BDM Firmware
LOOKUP TABLE
Secured BDM Firmware
LOOKUP TABLE
Figure 7-1. BDM Block Diagram
7.2 External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode.
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
281