56858 Datasheet, PDF (49/64 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

4.13 JTAG Timing
JTAG Timing
Table 4-14 JTAG Timing^{1, 3}
Operating Conditions: V_SS = V_SSIO = V_SSA = 0 V, V_DD = 1.62-1.98V, V_DDIO = V_DDA = 3.0–3.6V, T_A = –40° to +120°C, C_L ≤ 50pF, f_op = 120MHz
Characteristic
Symbol
Min
Max
Unit
TCK frequency of operation²
TCK cycle time
TCK clock pulse width
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
DE assertion time
f_OP
DC
30
MHz
t_CY
33.3
—
ns
t_PW
16.6
—
ns
t_DS
3
—
ns
t_DH
3
—
ns
t_DV
—
12
ns
t_TS
—
10
ns
t_TRST
35
—
ns
t_DE
4T
—
ns
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz operation,
T = 8.33ns.
2. TCK frequency of operation must be less than 1/4 the processor rate.
3. Parameters listed are guaranteed by design.
V_IH
TCK
(Input)
V_M = V_IL + (V_IH – V_IL)/2
t_CY
t_PW
V_M
V_IL
t_PW
V_M
Figure 4-33 Test Clock Input Timing Diagram
56858 Technical Data, Rev. 6
Freescale Semiconductor
49