56858 Datasheet, PDF (33/64 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Reset, Stop, Wait, Mode Select, and Interrupt Timing
4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing^{1, 2}
Operating Conditions: V_SS = V_SSIO = V_SSA = 0 V, V_DD = 1.62-1.98V, V_DDIO = V_DDA = 3.0–3.6V, T_A = –40° to +120°C, C_L ≤ 50pF, f_op = 120MHz
Characteristic
Symbol Min
Max Unit See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
t_RAZ
Minimum RESET Assertion Duration³
t_RA
RESET Deassertion to First External Address Output
Edge-sensitive Interrupt Request Width
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State⁴
Delay from IRQA Assertion (exiting Stop) to External
Data Memory⁵
t_RDA
t_IRW
t_IDM
t_{IDM -FAST}
t_IG
t_{IG -FAST}
t_IRI
t_{IRI -FAST}
t_IW
Delay from IRQA Assertion (exiting Wait) to External
t_IF
Data Memory
Fast⁶
Normal⁷
RSTO pulse width⁸
normal operation
internal reset mode
t_RSTO
—
30
—
1T + 3
18T
14T
18T
14T
22T
18T
1.5T
18T
22ET
128ET
8ET
11
—
120T
—
—
—
—
—
—
—
—
—
—
—
—
ns
Figure 4-11
ns
Figure 4-11
ns
Figure 4-11
ns
Figure 4-12
ns
Figure 4-13
ns
Figure 4-13
ns
Figure 4-14
Figure 4-15
ns
Figure 4-15
ns
ns
Figure 4-16
—
—
1. In the formulas, T = clock cycle. For f_op = 120MHz operation and f_ipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and t_clk assumes the period of the source clock,
t_xtal, t_extal or t_osc.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
6. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is
requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes
one less cycle and t_clk will continue same value it had before stop mode was entered.
56858 Technical Data, Rev. 6
Freescale Semiconductor
33