56858 Datasheet, PDF (34/64 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

7. Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and t_clk will resume at the input clock source rate.
8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
RESET
A0–Axx,
D0–D15
CS,
RD, WR
t_RA
t_RAZ
t_RDA
First Fetch
First Fetch
Figure 4-11 Asynchronous Reset Timing
IRQA
IRQB
t_IRW
Figure 4-12 External Interrupt Timing (Negative-Edge-Sensitive)
A0–Axx,
CS,
RD, WR
IRQA,
IRQB
General
Purpose
I/O Pin
IRQA,
IRQB
First Interrupt Instruction Execution
t_IDM
a) First Interrupt Instruction Execution
t_IG
b) General Purpose I/O
Figure 4-13 External Level-Sensitive Interrupt Timing
56858 Technical Data, Rev. 6
34
Freescale Semiconductor