MCIMX35_10 Datasheet, PDF (47/148 Pages) Freescale Semiconductor, Inc – i.MX35 Applications Processors for Industrial and Consumer Products

Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
ID
Parameter
Symbol
Min. Max.
Unit
SD7
SD8
SD9
SD10
Address hold time
SDRAM access time
Data out hold time¹
Active to read/write command period
tAH
1.8
—
ns
tAC
—
6.47
ns
tOH
1.2
—
ns
tRC
10
—
clock
1 _{Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see}
Table 41 and Table 42.
NOTE
SDR SDRAM CLK parameters are measured from the 50% point—that is,
high is defined as 50% of signal value and low is defined as 50% of signal
value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 33 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
i.MX35 Applications Processors for Automotive Products, Rev. 8
Freescale Semiconductor
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