MCIMX35_10 Datasheet, PDF (113/148 Pages) Freescale Semiconductor, Inc – i.MX35 Applications Processors for Industrial and Consumer Products

Table 73. SJC Timing Parameters (continued)
ID
Parameter
All Frequencies
Unit
Min.
Max.
SJ11 TCK low to TDO high impedance
SJ12 TRST assert time
SJ13 TRST set-up time to TCK low
—
44
ns
100
—
ns
40
—
ns
1 _{On cases where SDMA TAP is put in the chain, the max. TCK frequency is limited by max. ratio of 1:8 of SDMA core frequency}
to TCK limitation. This implies max. frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
2 _{VM = mid point voltage}
4.9.21 SPDIF Timing
SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by
a clock that is twice the bit rate of the data signal.
Figure 91 shows SPDIF timing parameters, including the timing of the modulating Rx clock (SRCK) for
SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK). for SPDIF in Tx mode.
Table 74. SPDIF Timing Parameters
Parameters
SPDIFIN Skew: asynchronous inputs, no specs apply
SPDIFOUT output (Load = 50 pf)
• Skew
• Transition rising
• Transition falling
SPDIFOUT1 output (Load = 30 pf)
• Skew
• Transition rising
• Transition falling
Modulating Rx clock (SRCK) period
SRCK high period
SRCK low period
Modulating Tx clock (STCLK) period
STCLK high period
STCLK low period
Symbol
—
Timing Parameter Range
Min.
—
Max.
0.7
—
—
1.5
—
—
24.2
—
—
31.3
—
—
1.5
—
—
13.6
—
—
18.0
srckp
40.0
—
srckph
16.0
—
srckpl
16.0
—
stclkp
40.0
—
stclkph
16.0
—
stclkpl
16.0
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
i.MX35 Applications Processors for Automotive Products, Rev. 8
Freescale Semiconductor
113