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MC9S12C_10 Datasheet, PDF (461/690 Pages) Freescale Semiconductor, Inc – Reference Manual | |||
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Chapter 15 Timer Module (TIM16B8CV1) Block Description
15.4.6 Gated Time Accumulation Mode
Setting the PAMOD bit conï¬gures the pulse accumulator for gated time accumulation operation. An active
level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE
bit selects low levels or high levels to enable the divided-by-64 clock.
The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF ï¬ag to
generate interrupt requests.
The pulse accumulator counter register reï¬ect the number of pulses from the divided-by-64 clock since the
last reset.
NOTE
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
15.5 Resets
The reset state of each individual bit is listed within Section 15.3, âMemory Map and Register Deï¬nitionâ
which details the registers and their bit ï¬elds.
15.6 Interrupts
This section describes interrupts originated by the TIM16B8CV1 block. Table 15-23 lists the interrupts
generated by the TIM16B8CV1 to communicate with the MCU.
Table 15-23. TIM16B8CV1 Interrupts
Interrupt
Offset
(1)
Vector1
Priority1
Source
Description
C[7:0]F
â
â
â
Timer Channel 7â0
Active high timer channel interrupts 7â0
PAOVI
â
â
PAOVF
â
â
â
Pulse Accumulator Active high pulse accumulator input interrupt
Input
â
Pulse Accumulator
Overï¬ow
Pulse accumulator overï¬ow interrupt
TOF
â
â
â
Timer Overï¬ow
1. Chip Dependent.
Timer Overï¬ow interrupt
The TIM16B8CV1 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
15.6.1 Channel [7:0] Interrupt (C[7:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 â 0 interrupt to be
serviced by the system controller.
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
461
Rev 01.24
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