MC9S12C_10 Datasheet, PDF (285/690 Pages) Freescale Semiconductor, Inc – Reference Manual

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
writes (0x0055 or 0x00AA) to the ARMCOP register must occur in the last 25% of the selected time-out
period. A premature write the CRG will immediately generate a reset.
As soon as the reset sequence is completed the reset generator checks the reset condition. If no clock
monitor failure is indicated and the latched state of the COP timeout is true, processing begins by fetching
the COP vector.
9.5.3 Power-On Reset, Low Voltage Reset
The on-chip voltage regulator detects when V_DD to the MCU has reached a certain level and asserts power-
on reset or low voltage reset or both. As soon as a power-on reset or low voltage reset is triggered the CRG
performs a quality check on the incoming clock signal. As soon as clock quality check indicates a valid
oscillator clock signal the reset sequence starts using the oscillator clock. If after 50 check windows the
clock quality check indicated a non-valid oscillator clock the reset sequence starts using self-clock mode.
Figure 9-26 and Figure 9-27 show the power-up sequence for cases when the RESET pin is tied to V_DD
and when the RESET pin is held low.
RESET
Clock Quality Check
(no Self-Clock Mode)
)(
Internal POR
Internal RESET
)(
128 SYSCLK
)(
64 SYSCLK
Figure 9-26. RESET Pin Tied to V_DD (by a Pull-Up Resistor)
RESET
Clock Quality Check
(no Self-Clock Mode)
)(
Internal POR
Internal RESET
)(
128 SYSCLK
)(
64 SYSCLK
Figure 9-27. RESET Pin Held Low Externally
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
285
Rev 01.24