MC9S12C_10 Datasheet, PDF (248/690 Pages) Freescale Semiconductor, Inc – Reference Manual

Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
8.5.1.3 Step 3
Configure how many conversions you want to perform in one sequence and define other settings in
ATDCTL3.
Example: Write S4C=1 to do 4 conversions per sequence.
8.5.1.4 Step 4
Configure resolution, sampling time and ATD clock speed in ATDCTL4.
Example: Use default for resolution and sampling time by leaving SRES8, SMP1 and SMP0 clear. For a
bus clock of 40MHz write 9 to PR4-0, this gives an ATD clock of 0.5*40MHz/(9+1) = 2MHz which is
within the allowed range for f_ATDCLK.
8.5.1.5 Step 5
Configure starting channel, single/multiple channel, continuous or single sequence and result data format
in ATDCTL5. Writing ATDCTL5 will start the conversion, so make sure your write ATDCTL5 in the last
step.
Example: Leave CC,CB,CA clear to start on channel AN0. Write MULT=1 to convert channel AN0 to
AN3 in a sequence (4 conversion per sequence selected in ATDCTL3).
8.5.2 Aborting an A/D conversion
8.5.2.1 Step 1
Disable the ATD Interrupt by writing ASCIE=0 in ATDCTL2. This will also abort any ongoing conversion
sequence.
It is important to clear the interrupt enable at this point, prior to step 3, as depending on the device clock
gating it may not always be possible to clear it or the SCF flag once the module is disabled (ADPU=0).
8.5.2.2 Step 2
Clear the SCF flag by writing a 1 in ATDSTAT0.
(Remaining flags will be cleared with the next start of a conversions, but SCF flag should be cleared to
avoid SCF interrupt.)
8.5.2.3 Step 3
Power down ATD by writing ADPU=0 in ATDCTL2.
8.6 Resets
At reset the ATD10B8C is in a power down state. The reset state of each individual bit is listed within
Section 8.3.2, “Register Descriptions” which details the registers and their bit-field.
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MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24