MC9S12C_10 Datasheet, PDF (20/690 Pages) Freescale Semiconductor, Inc – Reference Manual

Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.1.3 Block Diagram
V_SSR
V_DDR
V_DDX
V_SSX
V_DD2
V_SS2
V_DD1
V_SS1
BKGD
XFC
V_DDPLL
V_SSPLL
EXTAL
XTAL
RESET
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
TEST/V_PP
Voltage Regulator
16K, 32K, 64K, 96K, 128K Byte Flash
1K, 2K, 4K Byte RAM
MODC/TAGHI
BDM
HCS12
CPU
Clock and
PLL
Reset
Generation
Module
COP Watchdog
Clock Monitor
Periodic Interrupt
XIRQ
IRQ
R/W
LSTRB/TAGLO
ECLK
MODA/IPIPE0
MODB/IPIPE1
NOACC/XCLKS
System
Integration
Module
(SIM)
ATD
IOC0
IOC1
IOC2
Timer
IOC3
Module _IOC4
IOC5
IOC6
IOC7
PW0
PW1
PWM
PW2
Module
PW3
PW4
PW5
V_DDA
V_SSA
V_RH
V_RL
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
MUX
Multiplexed Address/Data Bus
DDRA
PTA
DDRB
PTB
SCI
RXD
TXD
MSCAN is not available on the
9S12GC Family Members
MSCAN
RXCAN
TXCAN
MISO
SPI
SS
MOSI
SCK
V_DDA
V_SSA
V_RH
V_RL
PAD0
PAD1
PAD2
PAD3
PAD4
PAD5
PAD6
PAD7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
PP0
PP1
PP2
PP3
PP4
PP5
PP6
PP7
PJ6
PJ7
PS0
PS1
PS2
PS3
PM0
PM1
PM2
PM3
PM4
PM5
Multiplexed
Wide Bus
Internal Logic 2.5V
V_DD1,2
V_SS1,2
PLL 2.5V
V_DDPLL
V_SSPLL
I/O Driver 5V
V_DDX
V_SSX
A/D Converter 5V
V_DDA
V_SSA
Signals shown in Bold are not available on the 52 or 48 Pin Package
Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package
Voltage Regulator 5V & I/O
V_DDR
V_SSR
V_RL is bonded internally to V_SSA
for 52- and 48-Pin packages
Figure 1-1. MC9S12C-Family / MC9S12GC-Family Block Diagram
20
MC9S12C-Family / MC9S12GC-Family
Freescale Semiconductor
Rev 01.24