56F8345_07 Datasheet, PDF (44/172 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Table 4-5 Interrupt Vector Table Contents¹ (Continued)
Peripheral
Vector
Number
Priority Vector Base
Level
Address +
Interrupt Function
TMRB
60
0-2
P:$78
Timer B, Channel 0
TMRB
61
0-2
P:$7A
Timer B, Channel 1
TMRB
62
0-2
P:$7C
Timer B, Channel 2
TMRB
63
0-2
P:$7E
Timer B, Channel 3
TMRA
64
0-2
P:$80
Timer A, Channel 0
TMRA
65
0-2
P:$82
Timer A, Channel 1
TMRA
66
0-2
P:$84
Timer A,Channel 2
TMRA
67
0-2
P:$86
Timer A, Channel 3
SCI0
68
0-2
P:$88
SCI 0 Transmitter Empty
SCI0
69
0-2
P:$8A
SCI 0 Transmitter Idle
Reserved
SCI0
71
0-2
P:$8E
SCI 0 Receiver Error
SCI0
72
0-2
P:$90
SCI 0 Receiver Full
ADCB
73
0-2
P:$92
ADC B Conversion Compete / End of Scan
ADCA
74
0-2
P:$94
ADC A Conversion Complete / End of Scan
ADCB
75
0-2
P:$96
ADC B Zero Crossing or Limit Error
ADCA
76
0-2
P:$98
ADC A Zero Crossing or Limit Error
PWMB
77
0-2
P:$9A
Reload PWM B
PWMA
78
0-2
P:$9C
Reload PWM A
PWMB
79
0-2
P:$9E
PWM B Fault
PWMA
80
0-2
P:$A0
PWM A Fault
core
81
-1
P:$A2
SW Interrupt LP
1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced
from the vector table, providing only 19 bits of address.
2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are
the chip reset addresses; therefore, these locations are not interrupt vectors.
56F8345 Technical Data, Rev. 17
44
Freescale Semiconductor
Preliminary