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56F8345_07 Datasheet, PDF (108/172 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers | |||
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6.5.1.3 Software Reset (SW RST)âBit 4
This bit is always read as 0. Writing 1 to this field will cause the part to reset.
6.5.1.4 Stop Disable (STOP_DISABLE)âBits 3â2
⢠00 = Stop mode will be entered when the 56800E core executes a STOP instruction
⢠01 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can be
reprogrammed in the future
⢠10 = The 56800E STOP instruction will not cause entry into Stop mode; STOP_DISABLE can then only be
changed by resetting the device
⢠11 = Same operation as 10
6.5.1.5 Wait Disable (WAIT_DISABLE)âBits 1â0
⢠00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
⢠01 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can be
reprogrammed in the future
⢠10 = The 56800E WAIT instruction will not cause entry into Wait mode; WAIT_DISABLE can then only
be changed by resetting the device
⢠11 = Same operation as 10
6.5.2 SIM Reset Status Register (SIM_RSTSTS)
Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A
reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this
register.
Base + $1
15 14 13 12 11 10
9
8
7
6
5
4
3
2 10
Read
Write
0
0
0
0
0
0
0
0
0
0
0
0
SWR COPR EXTR POR
RESET
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-4 SIM Reset Status Register (SIM_RSTSTS)
6.5.2.1 ReservedâBits 15â6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.2.2 Software Reset (SWR)âBit 5
When 1, this bit indicates that the previous reset occurred as a result of a software reset (write to SW RST
bit in the SIM_CONTROL register). This bit will be cleared by any hardware reset or by software. Writing
a 0 to this bit position will set the bit, while writing a 1 to the bit will clear it.
6.5.2.3 COP Reset (COPR)âBit 4
When 1, the COPR bit indicates the Computer Operating Properly (COP) timer-generated reset has
occurred. This bit will be cleared by a Power-On Reset or by software. Writing a 0 to this bit position will
56F8345 Technical Data, Rev. 17
108
Freescale Semiconductor
Preliminary
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