56F8345_07 Datasheet, PDF (107/172 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Register Descriptions
Add. Register
Offset Name
$0
SIM_
R
CONTROL _W
$1
SIM_
R
RSTSTS
W
R
$2
SIM_SCR0
W
R
$3
SIM_SCR1
W
R
$4
SIM_SCR2
W
R
$5
SIM_SCR3
W
$6
SIM_MSH_ ^R
ID
W
$7
SIM_LSH_ID ^R
W
R
$8
SIM_PUDR
W
Reserved
$A
SIM_
R
CLKOSR _W
R
$B
SIM_GPS
W
R
$C
SIM_PCE
W
R
$D
SIM_ISALH
W
R
$E
SIM_ISALL
W
15 14 13 12 11 10 9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
7
0
0
0
0
FIELD
6
5
4
3
2
1
0
0 _{ONCE SW}
EBL0 RST
STOP_
DISABLE
WAIT_
DISABLE
0
0
0
SWR COPR EXTR POR
FIELD
FIELD
FIELD
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
PWMA1
CAN
EMI_
MODE
RESET
IRQ
XBOOT PWMB PWMA0
0
CTRL
0
0
JTAG
0
0
0
0
0
0
0
0
A23 A22 A21 A20 CLKDIS
CLKOSEL
0
0
0
0
0
0
0
0
0
0
0
0
C3
C2
C1
C0
EMI ADCB ADCA CAN DEC1 DEC 0 TMRD TMRC TMRB TMRA SCI1 SCI0 SPI1 SPI0 PWMB PWMA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ISAL[23:22]
ISAL[21:6]
= Reserved
Figure 6-2 SIM Register Map Summary
6.5.1 SIM Control Register (SIM_CONTROL)
Base + $0
Read
Write
RESET
15 14 13 12 11 10 9 8 7 6
5
4
3
2
0
0
0
0
0
0
0
0
0
0 _{ONCE SW}
STOP_
EBL RST DISABLE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-3 SIM Control Register (SIM_CONTROL)
1
0
WAIT_
DISABLE
0
0
6.5.1.1 Reserved—Bits 15–6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.1.2 OnCE Enable (OnCE EBL)—Bit 5
• 0 = OnCE clock to 56800E core enabled when core TAP is enabled
• 1 = OnCE clock to 56800E core is always enabled
56F8345 Technical Data, Rev. 17
Freescale Semiconductor
107
Preliminary