MC9S08LL64_10 Datasheet, PDF (4/44 Pages) Freescale Semiconductor, Inc – Technical Data

V_DDA
V_SSA
♦ _VREFH
♦ _VREFL
V_DD
V_SS
• _VREFO1
♦ VREFO2
V_LCD
V_LL1
V_LL2
V_LL3
V_CAP1
V_CAP2
LCD[43:0]
HCS08 CORE
CPU
INT
ON-CHIP ICE
DEBUG MODULE (DBG)
BKGD
BKP
TIME OF DAY MODULE
(TOD)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
BKGD/MS
COP
RESET
IRQ
IRQ
LVD
8-BIT KEYBOARD
INTERRUPT (KBI)
SERIAL PERIPHERAL
INTERFACE (SPI)
IIC MODULE (IIC)
USER FLASH A
(LL64 = 32,768 BYTES)
(LL36 = 24,576 BYTES)
USER FLASH B
(LL64 = 32,768 BYTES)
(LL36 = 12,288 BYTES)
2-CHANNEL TIMER/PWM
(TPM2)
2-CHANNEL TIMER/PWM
(TPM1)
USER RAM
4 KB
SERIAL COMMUNICATIONS
INTERFACE (SCI1)
KBI[7:0]
SS
SPSCK
MISO
MOSI
SCL
SDA
TPM2CH0
TPM2CH1
TCLK
TPM1CH0
TPM1CH1
TCLK
TxD1
RxD1
INTERNAL CLOCK
SOURCE (ICS)
XTAL
LOW-POWER OSCILLATOR ^EXTAL
SERIAL COMMUNICATIONS
INTERFACE (SCI2)
12-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
TxD2
RxD2
ADP[11:4]
ADP0 •
ADP12 _•
PTA7/KBIP7/ADP11/ACMP–
PTA6/KBIP6/ADP10/ACMP+
PTA5/KBIP5/ADP9/LCD42
PTA4/KBIP4/ADP8/LCD43
PTA3/KBIP3/SCL/MOSI/ADP7
PTA2/KBIP2/SDA/MISO/ADP6
PTA1/KBIP1/SPSCK/ADP5
PTA0/KBIP0/SS/ADP4
PTB7/TxD2/SS
PTB6/RxD2/SPSCK
PTB5/MOSI/SCL
PTB4/MISO/SDA
PTB2/RESET ∞
PTB1/XTAL
PTB0/EXTAL
PTC7/IRQ/TCLK
PTC6/ACMPO//BKGD/MS ◊
PTC5/TPM2CH1
PTC4/TPM2CH0
PTC3/TPM1CH1
PTC2/TPM1CH0
PTC1/TxD1
PTC0/RxD1
ADP0 ^•
ADP12 •
VOLTAGE
REGULATOR
VREF1
VREF2
LIQUID CRYSTAL
DISPLAY
(LCD)
PTD[7:0]/LCD[7:0]
ANALOG COMPARATOR
(ACMP)
ACMP–
ACMP+
NOTES
ACMPO
PTE[7:0]/LCD[13:20]
• Pins are not available on 64-pin packages. LCD[8:12] and LCD[31:37] are
not available on the 64-pin package.
♦ V_REFH and V_REFL are internally connected to V_DDA and V_SSA for the 64-pin
package. VREFO2 is available only on the 64-pin package.
∞ When PTB2 is configured as RESET, the pin becomes bi-directional with
output being an open-drain drive.
◊ When PTC6 is configured as BKGD, the pin becomes bi-directional.
Figure 1. MC9S08LL64 Series Block Diagram
MC9S08LL64 Series MCU Data Sheet, Rev. 5
4
Freescale Semiconductor