MC9S08LL64_10 Datasheet, PDF (30/44 Pages) Freescale Semiconductor, Inc – Technical Data

AC Characteristics
3.10.3 SPI Timing
Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system.
Table 15. SPI Timing
No. C
Function
Operating frequency
— D Master
Slave
SPSCK period
1
D
Master
Slave
Enable lead time
2
D
Master
Slave
Enable lag time
3
D
Master
Slave
Clock (SPSCK) high or low time
4
D
Master
Slave
Data setup time (inputs)
5
D
Master
Slave
Data hold time (inputs)
6
D
Master
Slave
Symbol
f_op
t_SPSCK
t_Lead
t_Lag
t_WSPSCK
t_SU
t_HI
Min
Max
f_Bus/2048
0
2
4
1/2
1
1/2
1
t_cyc – 30
t_cyc – 30
15
15
0
25
f_Bus/2
f_Bus/4
2048
—
—
—
—
—
1024 t_cyc
—
—
—
—
—
Unit
Hz
t_cyc
t_cyc
t_SPSCK
t_cyc
t_SPSCK
t_cyc
ns
ns
ns
ns
ns
ns
7
D Slave access time
t_a
—
1
t_cyc
8
D Slave MISO disable time
Data valid (after SPSCK edge)
9
D
Master
Slave
Data hold time (outputs)
10 ^D
Master
Slave
Rise time
11 ^D
Input
Output
Fall time
12 ^D
Input
Output
t_dis
—
1
t_cyc
t_v
—
25
ns
—
25
ns
t_HO
0
0
—
ns
—
ns
t_RI
—
t_cyc – 25
ns
t_RO
—
25
ns
t_FI
—
t_cyc – 25
ns
t_FO
—
25
ns
MC9S08LL64 Series MCU Data Sheet, Rev. 5
30
Freescale Semiconductor