MC908MR16CBE Datasheet, PDF (37/282 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document.

Table 2-1. Vector Addresses (Continued)
Address
$FFEE
$FFEF
$FFF0
$FFF1
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
$FFF8
$FFF9
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
Vector
PWMMC vector (high)
PWMMC vector (low)
FAULT 4 (high)
FAULT 4 (low)
FAULT 3 (high)
FAULT 3 (low)
FAULT 2 (high)
FAULT 2 (low)
FAULT 1 (high)
FAULT 1 (low)
PLL vector (high)
PLL vector (low)
IRQ vector (high)
IRQ vector (low)
SWI vector (high)
SWI vector (low)
Reset vector (high)
Reset vector (low)
Monitor ROM
2.6 Monitor ROM
The 240 bytes at addresses $FE10–$FEFF are reserved ROM addresses that contain the instructions for
the monitor functions. See 18.3 Monitor ROM (MON).
2.7 Random-Access Memory (RAM)
Addresses $0060–$035F are RAM locations. The location of the stack RAM is programmable. The 16-bit
stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page
zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing mode instructions can access
efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the
contents of the CPU registers.
NOTE
For M68HC05 and M1468HC05 compatibility, the H register is not stacked.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
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