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MC908MR16CBE Datasheet, PDF (269/282 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. | |||
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Serial Peripheral Interface Characteristics
19.8 Serial Peripheral Interface Characteristics
Diagram
Number(1)
Characteristic(2)
Symbol
Min
Max
Unit
Operating frequency
Master
Slave
fOP(M)
fOP(S)
fOP/128
dc
fOP/2
fOP
MHz
Cycle time
1
Master
Slave
2
Enable lead time
3
Enable lag time
tCYC(M)
2
128
tCYC
tCYC(S)
1
â
tLead(S)
15
â
ns
tLag(S)
15
â
ns
Clock (SPCK) high time
4
Master
Slave
tSCKH(M)
100
tSCKH(S)
50
â
ns
â
Clock (SPCK) low time
5
Master
Slave
tSCKL(M)
100
tSCKL(S)
50
â
ns
â
Data setup time (inputs)
6
Master
Slave
tSU(M)
tSU(S)
45
5
â
â
ns
Data hold time (inputs)
7
Master
Slave
tH(M)
tH(S)
0
15
â
â
ns
Access time, slave(3)
8
CPHA = 0
CHPA = 1
tA(CP0)
tA(CP1)
0
0
40
20
ns
9
Disable time, slave(4)
tDIS(S)
â
25
ns
Data valid time after enable edge
10
Master
Slave(5)
tV(M)
tV(S)
â
10
ns
â
40
1. VDD = 5.0 Vdc ± 10%, all timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted; assumes 100 pF
load on all SPI pins
2. Numbers refer to dimensions in Figure 19-1 and Figure 19-2.
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
MC68HC908MR32 ⢠MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
269
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