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MC908MR16CBE Datasheet, PDF (247/282 Pages) Freescale Semiconductor, Inc – The following revision history table summarizes changes contained in this document. | |||
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I/O Registers
17.7.4 TIMB Channel Status and Control Registers
Each of the TIMB channel status and control registers:
⢠Flags input captures and output compares
⢠Enables input capture and output compare interrupts
⢠Selects input capture, output compare, or PWM operation
⢠Selects high, low, or toggling output on output compare
⢠Selects rising edge, falling edge, or any edge as the active input capture trigger
⢠Selects output toggling on TIMB overflow
⢠Selects 0 percent and 100 percent PWM duty cycle
⢠Selects buffered or unbuffered output compare/PWM operation
Register Name and Address:
Bit 7
6
Read: CH0F
Write: 0
CH0IE
Reset: 0
0
TBSC0 â $0056
5
4
MS0B MS0A
0
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Register Name and Address:
TBSC1 â $0059
Bit 7
6
5
4
Read: CH1F
0
CH1IE
MS1A
Write: 0
R
Reset: 0
0
0
0
R
= Reserved
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Figure 17-8. TIMB Channel Status and Control Registers (TBSC0âTBSC1)
CHxF â Channel x Flag
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMB counter registers matches the value in the TIMB channel x registers.
When CHxIE = 1, clear CHxF by reading TIMB channel x status and control register with CHxF set,
and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to
inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE â Channel x Interrupt Enable Bit
This read/write bit enables TIMB CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MC68HC908MR32 ⢠MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor
247
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