MC9S08JE128 Datasheet, PDF (35/44 Pages) Freescale Semiconductor, Inc – Covers: MC9S08JE128 and MC9S08JE64

Preliminary Electrical Characteristics
2.12 SPI Characteristics
Table 21 and Figure 11 through Figure 14 describe the timing requirements for the SPI system.
Table 21. SPI Timing
No.¹
Characteristic²
Symbol
Min
Max
Unit
C
Operating frequency
1
f_op
Master
Slave
SPSCK period
2
Master
Slave
t_SPSCK
Enable lead time
3
Master
Slave
t_Lead
Enable lag time
4
t_Lag
Master
Slave
Clock (SPSCK) high or low time
t_WSPSCK
5
Master
Slave
Data setup time (inputs)
6
t_SU
Master
t_SU
Slave
f_Bus/2048
0
2
4
1/2
1
1/2
1
t_cyc – 30
t_cyc – 30
15
15
f_Bus/2
f_Bus/4
2048
—
—
—
—
—
1024 t_cyc
—
—
—
Hz
D
Hz
t_cyc
D
t_cyc
t_SPSCK
D
t_cyc
t_SPSCK
D
t_cyc
ns
D
ns
ns
D
ns
Data hold time (inputs)
t_HI
7
Master
t_HI
0
—
ns
D
Slave
25
—
ns
8 Slave access time³
9 Slave MISO disable time⁴
t_a
—
t_dis
—
1
t_cyc
D
1
t_cyc
D
Data valid (after SPSCK edge)
t_v
10
Master
Slave
—
25
ns
D
—
25
ns
Data hold time (outputs)
t_HO
11
Master
0
Slave
0
—
ns
D
—
ns
Rise time
12
Input
t_RI
Output
t_RO
—
t_cyc – 25
ns
D
—
25
ns
Fall time
13
Input
t_FI
Output
t_FO
—
t_cyc – 25
ns
D
—
25
ns
1 _{Numbers in this column identify elements in Figure 11 through Figure 14.}
2 _{All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing}
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
3 _{Time to data active from high-impedance state.}
4 _{Hold time to high-impedance state.}
Freescale Semiconductor
35
Non-Disclosure Agreement Required
Preliminary — Subject to Change