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MC9S08JE128 Datasheet, PDF (1/44 Pages) Freescale Semiconductor, Inc – Covers: MC9S08JE128 and MC9S08JE64 | |||
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Freescale Semiconductor
Data Sheet: Advanced Information
An Energy-Efficient Solution from Freescale
Document Number: MC9S08JE128
Rev. 3, 04/2010
MC9S08JE128 series
Covers: MC9S08JE128 and MC9S08JE64
â
8-Bit HCS08 Central Processor Unit (CPU)
â Up to 48-MHz CPU above 2.4 V, 40 MHz CPU above 2.1 V, and
20 MHz CPU above 1.8 V across temperature of -40°C to 105°C
â HCS08 instruction set with added BGND instruction
â Support for up to 32 interrupt/reset sources
On-Chip Memory
â 128 K Dual Array Flash read/program/erase over full operating
voltage and temperature
â 12 KB Random-access memory (RAM)
â Security circuitry to prevent unauthorized access to RAM and
Flash
Power-Saving Modes
â Two ultra-low power stop modes. Peripheral clock enable register
can disable clocks to unused modules to reduce currents
â Time of Day (TOD) â Ultra-low power 1/4 sec counter with up to
64s timeout.
â Ultra-low power external oscillator that can be used in stop modes
to provide accurate clock source to the TOD. 6 usec typical wake
up time from stop3 mode
Clock Source Options
â Oscillator (XOSC1) â Loop-control Pierce oscillator; 32.768 kHz
crystal or ceramic resonator dedicated for TOD operation.
â Oscillator (XOSC2) â for high frequency crystal input for MCG
reference to be used for system clock and USB operations.
â Multipurpose Clock Generator (MCG) â PLL and FLL; precision
trimming of internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports CPU
frequencies from 4 kHz to 48 MHz.
System Protection
â Watchdog computer operating properly (COP) reset Watchdog
computer operating properly (COP) reset with option to run from
dedicated 1-kHz internal clock source or bus clock
â Low-voltage detection with reset or interrupt; selectable trip points;
separate low-voltage warning with optional interrupt; selectable
trip points
â Illegal opcode and illegal address detection with reset
â Flash block protection for each array to prevent accidental
write/erasure
â Hardware CRC to support fast cyclic redundancy checks
Development Support
â Single-wire background debug interface
â Real-time debug with 6 hardware breakpoints (4 PC, 1 address
and 1 data) Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
â On-chip in-circuit emulator (ICE) debug module containing 3
comparators and 9 trigger modes
Peripherals
â CMTâ Carrier Modulator timer for remote control
communications. Carrier generator, modulator and driver for
dedicated infrared out. Can be used as an output compare timer.
â IICâ Up to 100 kbps with maximum bus loading; Multi-master
operation; Programmable slave address; Interrupt driven
64-LQFP 10mm x 10mm
80-LQFP 12mm x 12mm
81-MapBGA 10mm x10mm
byte-by-byte data transfer; supports broadcast mode and 11-bit
addressing
â PRACMP â Analog comparator with selectable interrupt;
compare option to programmable internal reference voltage;
operation in stop3
â SCI â Two serial communications interfaces with optional 13-bit
break; option to connect Rx input to PRACMP output on SCI1 and
SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from
stop3 on Rx edge
â SPI1â Serial peripheral interface (SPI) with 64-bit FIFO buffer;
16-bit or 8-bit data transfers; full-duplex or single-wire
bidirectional; double-buffered transmit and receive; master or
slave mode; MSB-first or LSB-first shifting
â SPI2â Serial peripheral interface with full-duplex or single-wire
bidirectional; Double-buffered transmit and receive; Master or
Slave mode; MSB-first or LSB-first shifting
â TPM â Two 4-channel Timer/PWM Module; Selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel; external clock input/pulse accumulator
â USB â Supports USB in full-speed device configuration. On-chip
transceiver and 3.3V regulator help save system cost, fully
compliant with USB Specification 2.0. Allows control, bulk,
interrupt and isochronous transfers.
â ADC12 â 12-bit Successive approximation ADC with up to 4
dedicated differential channels and 8 single-ended channels;
range compare function; 1.7 mV/°C temperature sensor; internal
bandgap reference channel; operation in stop3; fully functional
from 3.6V to 1.8V, Configurable hardware trigger for 8 Channel
select and result registers
â PDB â Programmable delay block with 16-bit counter and
modulus and prescale to set reference clock to bus divided by 1 to
bus divided by 2048; 8 trigger outputs for ADC12 module provides
periodic coordination of ADC sampling sequence with sequence
completion interrupt; Back-to-Back mode and Timed mode
â DAC â 12-bit resolution; 16-word data buffers with configurable
watermark.
Input/Output
â Up to 47 GPIOs and 2 output-only pin and 1 input-only pin.
â Voltage Reference output (VREFO).
â Dedicated infrared output pin (IRO) with high current sink
capability.
â Up to 16 KBI pins with selectable polarity.
Package Options
â 81-MBGA 10x10 mm
â 80-LQFP 12x12 mm
â 64-LQFP 10x10 mm
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Non-Disclosure Agreement Required
Preliminary â Subject to Change
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