K40P144M100SF2_11 Datasheet, PDF (33/75 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 19. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
t_eewr16bers Word-write to erased FlexRAM location
execution time
—
100
Word-write to FlexRAM execution time:
t_eewr16b32k
t_eewr16b64k
t_eewr16b128k
t_eewr16b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
TBD
—
TBD
—
TBD
—
TBD
Longword-write to FlexRAM for EEPROM operation
t_eewr32bers Longword-write to erased FlexRAM location
execution time
—
200
Longword-write to FlexRAM execution time:
t_eewr32b32k
t_eewr32b64k
t_eewr32b128k
t_eewr32b256k
• 32 KB EEPROM backup
• 64 KB EEPROM backup
• 128 KB EEPROM backup
• 256 KB EEPROM backup
—
TBD
—
TBD
—
TBD
—
TBD
Max.
TBD
TBD
1.5
TBD
2.5
TBD
TBD
2.7
TBD
3.7
Unit
Notes
μs
ms
ms
ms
ms
μs
ms
ms
ms
ms
1. Assumes 25MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.
6.4.1.3 Flash (FTFL) current and power specfications
Table 20. Flash (FTFL) current and power specfications
Symbol
I_{DD_PGM}
Description
Worst case programming current in program flash
Typ.
Unit
10
mA
6.4.1.4 Reliability specifications
Table 21. NVM reliability specifications
Symbol Description
t_nvmretp10k Data retention after up to 10 K cycles
t_nvmretp1k Data retention after up to 1 K cycles
t_nvmretp100 Data retention after up to 100 cycles
n_nvmcycp Cycling endurance
t_nvmretd10k Data retention after up to 10 K cycles
Min.
Program Flash
5
10
15
10 K
Data Flash
5
Typ.¹
TBD
TBD
TBD
TBD
TBD
Max.
—
—
—
—
—
Table continues on the next page...
Unit
years
years
years
cycles
years
Notes
2
2
2
3
2
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
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