K40P144M100SF2_11 Datasheet, PDF (27/75 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

Peripheral operating requirements and behaviors
Table 13. MCG specifications (continued)
Symbol Description
Min.
I_intf
Internal reference (fast clock) current
—
t_irefstf Internal reference startup time (fast clock)
—
f_{loc_low}
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
f_{ints_t}
f_{loc_high} Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
f_{ints_t}
FLL
f_{fll_ref} FLL reference frequency range
31.25
f_dco
DCO output
Low range (DRS=00)
20
frequency range
640 × f_{fll_ref}
Mid range (DRS=01)
40
1280 × f_{fll_ref}
Mid-high range (DRS=10)
60
1920 × f_{fll_ref}
High range (DRS=11)
80
2560 × f_{fll_ref}
f_{dco_t_DMX3} DCO output
2
frequency
Low range (DRS=00)
—
732 × f_{fll_ref}
Mid range (DRS=01)
—
1464 × f_{fll_ref}
Mid-high range (DRS=10)
—
2197 × f_{fll_ref}
High range (DRS=11)
—
2929 × f_{fll_ref}
J_{cyc_fll} FLL period jitter
—
J_{acc_fll} FLL accumulated jitter of DCO output over a 1µs
—
time window
t_{fll_acquire} FLL target frequency acquisition time
—
PLL
f_vco
VCO operating frequency
48.0
I_pll
PLL operating current
• PLL @ 96 MHz (f_{osc_hi_1}=8MHz,
—
f_{pll_ref}=2MHz, VDIV multiplier=48)
f_{pll_ref} PLL reference frequency range
2.0
J_{cyc_pll} PLL period jitter
—
J_{acc_pll} PLL accumulated jitter over 1µs window
—
Typ.
TBD
TBD
—
—
Max.
—
TBD
—
—
—
20.97
39.0625
25
41.94
50
62.91
75
83.89
100
23.99
—
47.97
—
71.99
—
95.98
—
TBD
TBD
—
TBD
TBD
1
—
100
950
—
—
4.0
400
—
TBD
—
Unit
µA
µs
kHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ms
MHz
µA
MHz
ps
ps
Notes
2, 3
4, 5
6
6
7
8
9, 10
9, 10
Table continues on the next page...
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
27