K40P144M100SF2_11 Datasheet, PDF (20/75 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

General
5.2.1 Device clock specifications
Symbol
f_SYS
f_{SYS_USB}
f_BUS
FB_CLK
f_FLASH
f_SYS
f_BUS
FB_CLK
f_FLASH
Description
Normal run mode
System and core clock
System and core clock when USB in operation
Bus clock
FlexBus clock
Flash clock
VLPR mode
System and core clock
Bus clock
FlexBus clock
Flash clock
Min.
—
20
—
—
—
—
—
—
—
Max.
100
—
50
50
25
2
2
2
1
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I²C signals.
Symbol
Description
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
• Slew disabled
• Slew enabled
Port rise and fall time (low drive strength)
• Slew disabled
• Slew enabled
Min.
1.5
100
16
TBD
2
—
—
—
—
Max.
—
—
—
—
—
12
36
32
36
Unit
Bus clock
cycles
ns
ns
Bus clock
cycles
ns
ns
ns
ns
Notes
1
2
2
3
4
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75pF load
K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
20
Preliminary
Freescale Semiconductor, Inc.