MC9S08GW64_11 Datasheet, PDF (31/42 Pages) Freescale Semiconductor, Inc – HC08 instruction set with added BGND instruction

Electrical Characteristics
3.10.3 SPI Timing
Table 15 and Figure 20 through Figure 23 describe the timing requirements for the SPI system^1,2.
Table 15. SPI Timing
No. C
Function
—
Operating frequency
D Master
Slave
SPSCK period
1 ^{D Master}
Slave
Enable lead time
2 ^{D Master}
Slave
Enable lag time
3 ^{D Master}
Slave
Clock (SPSCK) high or low time
4 ^{D Master}
Slave
Data setup time (inputs)
5 ^{D Master}
Slave
Data hold time (inputs)
6 ^{D Master}
Slave
Slave access time
7
D
Slave MISO disable time
8
D
Data valid (after SPSCK edge)
9 ^{D Master}
Slave
Data hold time (outputs)
10 ^{D Master}
Slave
Rise time
11 ^{D Input}
Output
Fall time
12 ^{D Input}
Output
Symbol
f_op
t_SPSCK
t_Lead
t_Lag
t_WSPSCK
t_SU
t_HI
t_a
t_dis
t_v
t_HO
t_RI
t_RO
t_FI
t_FO
Min
Max
f_Bus/2048
0
2
4
12
1
12
1
t_cyc –30
t_cyc – 30
30
30
0
25
—
f_Bus/2
f_Bus/4
2048
—
—
—
—
—
1024 t_cyc
—
—
—
—
—
1
—
1
—
60
—
60
0
—
0
—
—
t_cyc – 25
—
25
—
t_cyc – 25
—
25
Unit
Hz
t_cyc
t_cyc
t_SPSCK
t_cyc
t_SPSCK
t_cyc
ns
ns
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
ns
ns
ns
ns
1.There is 20 pF load on the SPI ports.
2.There are three types of SPI ports in MC9S08GW64 Series. They are ports for AMR, ports shared with LCD pads
and normal ports. This timing is for normal ports condition.
MC9S08GW64 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
31