MC9S08GW64_11 Datasheet, PDF (1/42 Pages) Freescale Semiconductor, Inc – HC08 instruction set with added BGND instruction

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08GW64
Rev. 3, 1/2011
MC9S08GW64 Series
Covers: MC9S08GW64 and
MC9S08GW64 80-LQFP
Case 917A
64-LQFP
Case 840F
14  14
10  10
MC9S08GW32
8-Bit HCS08 Central Processor Unit (CPU)
comparator can be used as hardware breakpoint. Full mode,
Comparator A compares address and Comparator B compares data.
Supports both tag and force breakpoints
– New version of S08 core with same performace as traditional S08 and
lower power
– Up to 20 MHz CPU at 3.6 V to 2.15 V and up to 10 MHz CPU at 3.6 V
to 1.8 V, across temperature range of –40 C to 85 C
– HC08 instruction set with added BGND instruction
– Support for up to 48 interrupt/reset sources
On-Chip Memory
– Flash read/program/erase over full operating voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and flash
contents
Power-Saving Modes
– Two low power stop modes and reduced power wait mode
– Low power run and wait modes allow peripherals to run while voltage
regulator is in standby
– Peripheral clock gating register can disable clocks to unused modules,
thereby reducing currents
– Very low power external oscillator that can be used in stop2 or stop3
modes to provide accurate clock source to real time counter
– 6 s typical wakeup time from stop3 mode
Clock Source Options
– Oscillator (XOSC1) — Loop-control Pierce oscillator; Crystal or
ceramic resonator of 32.768 kHz; Clock source for iRTC or ICS
– Oscillator (XOSC2) — Loop-control Pierce oscillator; Crystal or
ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz;
optional clock source for ICS
– Internal Clock Source (ICS) — Internal clock source module
containing a frequency-locked-loop (FLL) controlled by internal or
external reference (XOSC1, XOSC2); precision trimming of internal
reference allows 0.2% resolution and 2% deviation over temperature
and voltage; supporting CPU/bus frequencies from 1 MHz to 20 MHz
System Protection
– Watchdog computer operating properly (COP) reset with option to run
from dedicated 1 kHz internal clock source or bus clock
– Low-voltage warning with interrupt
– Low-voltage detection with reset or interrupt
– Illegal opcode and illegal address detection with reset
– Flash block protection
Development Support
– Single-wire background debug interface
– Breakpoint capability to allow single breakpoint setting during
in-circuit debugging (plus 3 more breakpoints in breakpoint unit)
– Breakpoint (BKPT) debug module containing three comparators (A, B,
and C) with ability to match addresses in 64 KB space. Each
Peripherals
– LCD — up to 440 or 836 LCD driver with internal charge pump and
option to provide an internally regulated LCD reference that can be
trimmed for contrast control
– ADC16 — two analog-to-digital converters; 16-bit resolution; one
dedicated differential per ADC; up to 16-ch; up to 2.5 s conversion
time for 12-bit mode; automatic compare function; hardware
averaging; calibration registers; temperature sensor; internal bandgap
reference channel; operation in stop3; fully functional from 3.6 V to
1.8 V
– PRACMP —three rail to rail programmable reference analog
comparator; up to 8 inputs; on-chip programmable reference generator
output; selectable interrupt on rising, falling, or either edge of
comparator output; operation in stop3
– SCI — four full duplex non-return to zero (NRZ); LIN master extended
break generation; LIN slave extended break detection; wakeup on
active edge; SCI0 designed for AMR operation; TxD of SCI1 and SCI2
can be modulated with timers and RxD can recieved through
PRACMP;
– SPI— three full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first
shifting; SPI0 designed for AMR opeartion
– IIC — up to 100 kbps with maximum bus loading; multi-master
operation; programmable slave address; interrupt driven byte-by-byte
data transfer; supporting broadcast mode and 10-bit addressing;
supporting SM BUS functionality; can wake from stop3
– FTM — 2-channel flextimer module; selectable input capture, output
compare, or buffered edge- or center-aligned PWM on each channel
– IRTC — independent real-time clock, independent power domain, 32
bytes RAM, 32.768 kHz input clock optional output to ICS, hardware
calendar, hardware compensation due to crystal or temperature
characteristics, tamper detection and indicator
– PCRC — 16/32 bit programmable cyclic redundancy check for
high-speed CRC calculation
– MTIM — two 8-bit and one 16-bit timers; configurable clock inputs
and interrupt generation on overflow
– PDB — programmable delay block; optimized for scheduling ADC
conversions
– PCNT — position counter; working in stop3 mode without waking
CPU; can be used to generate waveforms like timer
Input/Output
– 57 GPIOs including one output-only pin
– Eight KBI interrupts with selectable polarity
– Hysteresis and configurable pullup device on all input pins;
configurable slew rate and drive strength on all output pins.
Package Options
– 80-pin LQFP, 64-pin LQFP
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2010-2011. All rights reserved.