K10P81M100SF2_11 Datasheet, PDF (31/64 Pages) Freescale Semiconductor, Inc – K10 Sub-Family Data Sheet Supports the following Flash write voltage range: 1.71 to 3.6 V

Num
EP5
EP6
EP7
EP8
EP9
Peripheral operating requirements and behaviors
Table 22. EzPort switching specifications (continued)
Description
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Min.
Max.
Unit
2
—
ns
5
—
ns
—
12
ns
0
—
ns
—
12
ns
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
EP7
EP8
EP5
EP6
Figure 9. EzPort Timing Diagram
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
Table 23. Flexbus switching specifications
Num
Description
Operating voltage
Frequency of operation
Min.
2.7
—
Max.
3.6
50
Unit
V
Mhz
Notes
Table continues on the next page...
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
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