MC9S08PT60 Datasheet, PDF (26/37 Pages) Freescale Semiconductor, Inc – MC9S08PT60

Peripheral operating requirements and behaviors
Table 14. SPI master mode timing (continued)
Nu Symbol Description
m.
6
t_SU
Data setup time (inputs)
7
t_HI
Data hold time (inputs)
8
t_v
Data valid (after SPSCK edge)
9
t_HO
Data hold time (outputs)
10
t_RI
Rise time input
t_FI
Fall time input
11
t_RO
Rise time output
t_FO
Fall time output
Min.
15
0
—
0
—
—
Max.
—
—
25
—
t_Bus - 25
25
Unit
ns
ns
ns
ns
ns
ns
SS¹
(OUTPUT)
3
2
10
SPSCK
(CPOL = 0)
5
(OUTPUT)
5
11
4
SPSCK
(CPOL = 1)
(OUTPUT)
10
11
6
7
MISO
(INPUT)
MSB IN²
BIT 6 . . . 1
LSB IN
MOSI
(OUTPUT)
MSB OUT²
8
BIT 6 . . . 1
9
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA=0)
Comment
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MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
26
Freescale Semiconductor, Inc.