MC9S08PT60 Datasheet, PDF (25/37 Pages) Freescale Semiconductor, Inc – MC9S08PT60

Peripheral operating requirements and behaviors
3. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
6.3.2 Analog comparator (ACMP) electricals
Table 13. Comparator electrical specifications
C
Characteristic
Symbol
D
Supply voltage
V_DDA
T
Supply current (Operation mode)
I_DDA
D
Analog input voltage
V_AIN
P
Analog input offset voltage
V_AIO
C Analog comparator hysteresis (HYST=0)
V_H
C Analog comparator hysteresis (HYST=1)
V_H
T
Supply current (Off mode)
I_DDAOFF
C
Propagation Delay
t_D
Min
2.7
—
V_SS - 0.3
—
—
—
—
—
Typical
—
10
—
—
15
20
60
0.4
Max
5.5
20
V_DDA
40
20
30
—
1
Unit
V
µA
V
mV
mV
mV
nA
µs
6.4 Communication interfaces
6.4.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of
the chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
V_DD and 70% V_DD, unless noted, and 100 pF load on all SPI pins. All timing assumes
slew rate control is disabled and high drive strength is enabled for SPI output pins.
Table 14. SPI master mode timing
Nu Symbol Description
m.
1
f_op
Frequency of operation
Min.
f_Bus/2048
Max.
f_Bus/2
2
t_SPSCK SPSCK period
3
t_Lead
Enable lead time
4
t_Lag
Enable lag time
5
t_WSPSCK Clock (SPSCK) high or low time
2 x t_Bus
1/2
1/2
t_Bus - 30
2048 x t_Bus
—
—
1024 x t_Bus
Table continues on the next page...
Unit
Hz
ns
t_SPSCK
t_SPSCK
ns
Comment
f_Bus is the bus
clock
t_Bus = 1/f_Bus
—
—
—
MC9S08PT60 Series Data Sheet, Rev. 3, 4/2012.
Freescale Semiconductor, Inc.
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