33984 Datasheet, PDF (24/38 Pages) Freescale Semiconductor, Inc – Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mOhm)

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
C_CSS B
S^SCC ^LL^KK
SI
SI
D7
D6
D5
S_SO_O
OD7
OD6
OD5
D2
D1
D0
D 7*
D 6*
D 5*
OD2
OD1
OD0
D7
D6
D5
D 2*
D 1*
D 0*
D2
D1
D0
Notes 1. is a Logic [1] state during the above operation. RST N O T E S : 1 .
2.
R^RS^ST ^{T B i s i n a l o g i c 1 s t a t e d u r i n g t h e a b o v e o p e r a t i o n .}
D 0 , D 1 , D 2 , ..., a n d D 7 re la te to th e m o s t re c e n t o rd e re d e n try o f d a ta in to th e S P S S
2.³ D^. 7 :^OD^D0⁰r^,e^Ola^Dte^{1 ,}to^O t^Dh²e^, m^{. . . ,}o^asⁿt ^dre^Oce^D n⁷ t ^ro^e r^{l a}d^te^e re^{t o}d^{t h}e^ent^fr^{i r}y^{s t}o⁸f d^b a^{i t s}ta^o i^fn^oto^{r d} t^eh^re^{e d}d^fe^av^ui^lc^t e^a.^{n d s t a t u s d a t a o u t o f t h e d e v i c e .}
4.
O D 0 , O D 1 , O D 2 , ..., a n d O D 7 re p re s e n t th e firs t 8 b its o f o rd e re d fa u lt a n d s ta tu s d a ta o u t o f th e S P S S
3. D7*:D0* relate to the previous 8 bits (last command word) of data that was previously shifted into the device.
4. OD7:OD0 relate to the first 8 bits of ordered fault and status data out of the device.
F IG U R E 4 b . M U L T IP L E 8 b it W O R D S P I C O M M U N IC A T IO N
Figure 10. Multiple 8-Bit Word SPI Communication
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 8-bit
messages. A message is transmitted by the MCU starting
with the MSB, D7, and ending with the LSB, D0 (Table 9).
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB (D7)
is the watchdog bit and in some cases a register address bit
common to both outputs or specific to an output; the next
three bits, D6 : D4, are used to select the command register;
and the remaining four bits, D3 : D0, are used to configure and
control the outputs and their protection features.
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of eight bits. Any attempt made to
latch in a message that is not eight bits will be ignored.
The 33984 has defined registers, which are used to
configure the device and to control the state of the output.
Table 10, summarizes the SI registers. The registers are
addressed via D6 : D4 of the incoming SPI word (Table 9).
Table 9. SI Message Bit Assignment
Bit Sig SI Msg Bit
Message Bit Description
MSB
LSB
D7
D6 : D4
D3 : D1
D0
Register address bit for output selection.
Also used for watchdog: toggled to satisfy
watchdog requirements.
Register address bits.
Used to configure the inputs, outputs, and
the device protection features and SO status
content.
Used to configure the inputs, outputs, and
the device protection features and SO status
content.
Table 10. Serial Input Address and Configuration Bit
Map
SI
Serial Input Data
Register _{D7 D6 D5 D4 D3}
D2
D1
D0
STATR s 0 0 0
0
SOA2 SOA1 SOA0
OCR x 0 0 1 CSNS1 IN1_SPI CSNS0 IN0_SPI
EN
EN
SOCHLR s 0 1 0 SOCHs SOCL2s SOCL1s SOCL0s
CDTOLR s 0 1 1 OL_DIS CD_DIS OCLT1s OCLT0s
s
s
DICR s 1 0 0 FAST CSNS IN DIS s A/Os
SR s high s
OSDR 0 1 0 1
0
WDR 1 1 0 1
0
NAR 0 1 1 0
0
OSD2
0
0
OSD1
WD1
0
OSD0
WD0
0
UOVR 1 1 1 0
0
0
UV_dis OV_dis
TEST x 1 1 1
Freescale Internal Use (Test)
x = Don’t care.
s (SOA3 bit) = Selection of output: Logic [0] = HS0, Logic [1] =
HS1.
33984
24
Analog Integrated Circuit Device Data
Freescale Semiconductor