33984 Datasheet, PDF (14/38 Pages) Freescale Semiconductor, Inc – Dual Intelligent High-current Self-protected Silicon High Side Switch (4.0 mOhm)

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.5 V ≤ V_DD ≤ 5.5 V, 6.0 V ≤ V_PWR ≤ 27 V, -40°C ≤ T_A ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Recommended Frequency of SPI Operation
f _SPI
–
Required Low State Duration for RST⁽²⁴⁾
t _WRST
–
Rising Edge of CS to Falling Edge of CS (Required Setup Time)⁽²⁵⁾
t _CS
–
Rising Edge of RST to Falling Edge of CS (Required Setup Time)⁽²⁵⁾
t _ENBL
–
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)⁽²⁵⁾
t _LEAD
–
Required High State Duration of SCLK (Required Setup Time)⁽²⁵⁾
t _WSCLKh
–
Required Low State Duration of SCLK (Required Setup Time)⁽²⁵⁾
t _WSCLKl
–
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)⁽²⁵⁾
t _LAG
–
SI to Falling Edge of SCLK (Required Setup Time)⁽²⁶⁾
t _SI(SU)
–
Falling Edge of SCLK to SI (Required Setup Time)⁽²⁶⁾
t _SI(HOLD)
–
SO Rise Time
C_L = 200 pF
t _RSO
–
SO Fall Time
C_L = 200 pF
SI, CS, SCLK, Incoming Signal Rise Time⁽²⁶⁾
SI, CS, SCLK, Incoming Signal Fall Time⁽²⁶⁾
Time from Falling Edge of CS to SO Low-impedance⁽²⁷⁾
Time from Rising Edge of CS to SO High-impedance⁽²⁸⁾
Time from Rising Edge of SCLK to SO Data Valid⁽²⁹⁾
0.2 x V_DD ≤ SO ≤ 0.8 x V_DD, C_L = 200 pF
t _FSO
–
t _RSI
–
t _RSI
–
t _SO(EN)
–
t _SO(DIS)
–
t _VALID
–
–
3.0
MHz
50
350
ns
–
300
ns
–
5.0
μs
50
167
ns
–
167
ns
–
167
ns
50
167
ns
25
83
ns
25
83
ns
ns
25
50
ns
25
50
–
50
ns
–
50
ns
–
145
ns
65
145
ns
ns
65
105
Notes
24. RST low duration measured with outputs enabled and going to OFF or disabled condition.
25. Maximum setup time required for the 33984 is the minimum guaranteed time needed from the microcontroller.
26. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
27. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
28. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
29. Time required to obtain valid data out from SO following the rise of SCLK.
33984
14
Analog Integrated Circuit Device Data
Freescale Semiconductor