MC9S08MP16 Datasheet, PDF (22/36 Pages) Freescale Semiconductor, Inc – 8-Bit HCS08 Central Processor Unit (CPU)

Electrical Characteristics
Table 10. ICS Frequency Specifications (Temperature Range = –40 to 105°C Ambient) (continued)
Num C
Characteristic
Symbol
Min Typ¹ Max Unit
P
Low range (DRS=00)
DCO output frequency range —
4 C _{trimmed 2}
Mid range (DRS=01)
P
High range (DRS=10)
f_{dco_t}
16
—
20
32
—
40 MHz
48
—
60
P _{DCO output frequency 2}
5 P _{Reference = 32768 Hz and}
P ^{DMX32 = 1}
Low range (DRS=00)
Mid range (DRS=01)
High range (DRS=10)
— 19.92 —
f_{dco_DMX32}
—
39.85
—
MHz
— 59.77 —
6
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (using FTRIM)
Δf_{dco_res_t}
—
± 0.1 ± 0.2 %f_dco
7
C
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (not using FTRIM)
Δf_{dco_res_t}
—
± 0.2 ± 0.4 %f_dco
8
C
Total deviation of trimmed DCO output frequency over voltage and
temperature
Δf_{dco_t}
—
± 0.8 ± 2 %f_dco
9
C
Total deviation of trimmed DCO output frequency over fixed voltage
and temperature range of 0°C to 70 °C
Δf_{dco_t}
—
± 0.5 ± 1 %f_dco
10 C _{FLL acquisition time} ³
t_Acquire
—
—
1
ms
11 C _{Long term jitter of DCO output clock (averaged over 2-ms interval)} ⁴ C_Jitter
—
0.02
0.2 %f_dco
1 _{Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.}
2 _{The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.}
3 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing}
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for a given
interval.
MC9S08MP16 Series Data Sheet, Rev. 1
22
Freescale Semiconductor