908E624 Datasheet, PDF (22/40 Pages) Freescale Semiconductor, Inc – Integrated Triple High-Side Switch with Embedded MCU and LIN Serial Communication for Relay Drivers

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 6. Operating Modes Overview
Device
Mode
Voltage Regulator
Reset
Normal
Request
V_DD ON
V_DD ON
Wake-Up
Capabilities
N/A
N/A
RST_A
Output
LOW
HIGH
Normal
(Run)
V_DD ON
N/A
HIGH
Stop
V_DD ON with limited
LIN wake-up,
current capability L1, L2 state change,
SS rising edge
HIGH
Sleep
V_DD OFF
LIN wake-up
L1, L2 state change
LOW
Watchdog
Function
Disabled
150 ms time out if
WD enabled
Window WD if
enabled
Disabled
HS1, HS2,
and HS3
LIN Interface
Sense
Amplifier
Disabled
Recessive only Not active
Enabled
Transmit and
receive
Not active
Enabled
Transmit and
receive
Active
Disabled Recessive state with Not active
wake-up capability
Disabled
Disabled Recessive state with Not active
wake-up capability
INTERRUPTS
In Normal (Run) mode the 908E624 has four different
interrupt sources. An interrupt pulse on the IRQ_A terminal is
generated to report a fault to the MCU. All interrupts are not
maskable and cannot be disabled.
After an Interrupt the INTSRC bit in the SPI Status register
is set, indicating the source of the event. This interrupt source
information is only transferred once, and the INTSRC bit is
cleared automatically.
Low-Voltage Interrupt
Low-voltage interrupt (LVI) is related to external supply
voltage VSUP1. If this voltage falls below the LVI threshold,
it will set the LVF bit in the SPI Status register and an interrupt
will be initiated. The LVF bit remains set as long as the Low-
voltage condition is present.
During Sleep and Stop mode the low-voltage interrupt
circuitry is disabled.
High-Voltage Interrupt
High-voltage interrupt (HVI) is related to external supply
voltage VSUP1. If this voltage rises above the HVI threshold,
it will set the HVF bit in the SPI Status register and an
interrupt will be initiated. The HVF bit remains set as long as
the high-voltage condition is present.
During Sleep and Stop mode the high-voltage interrupt
circuitry is disabled.
Wake-Up Interrupts
In Stop mode the IRQ_A terminal reports wake-up events
on the L1, L2, or the LIN bus to the MCU. All wake-up
interrupts are not maskable and cannot be disabled.
After a wake-up interrupt, the INTSRC bit in the Serial
Peripheral Interface (SPI) Status register is set, indicating the
source of the event. This wake-up source information is only
transferred once, and the INTSRC bit is cleared
automatically.
Figure 12, page 23, describes the Stop / Wake-Up
procedure.
Voltage Regulator Temperature Prewarning (VDDT)
Voltage regulator temperature prewarning (VDDT) is
generated if the voltage regulator temperature is above the
T_PRE threshold. It will set the VDDT bit in the SPI Status
register and an interrupt will be initiated. The VDDT bit
remains set as long as the error condition is present.
During Sleep and Stop mode the voltage regulator
temperature prewarning circuitry is disabled.
High-Side Switch Thermal Shutdown (HSST)
The high-side switch thermal shutdown HSST is
generated if one of the high-side switches HS1 : HS3 is above
the HSST threshold, it will shutdown all high-side switches,
set the HSST flag in the SPI Status register and an interrupt
will be initiated. The HSST bit remains set as long as the error
condition is present.
During Sleep and Stop mode the high-side switch thermal
shutdown circuitry is disabled.
908E624
22
Analog Integrated Circuit Device Data
Freescale Semiconductor