33982B Datasheet, PDF (22/34 Pages) Freescale Semiconductor, Inc – Single Intelligent High-Current Self-Protected Silicon High-Side Switch (2.0 mohm)

FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Table 9. Serial Input Address and Configuration Bit Map
SI
Serial Input Data
Register _{D7 D6 D5 D4 D3}
D2
D1
D0
STATR x 0 0 0 0 SOA2 SOA1 SOA0
OCR x 0 0 1 0
0
CSNS IN_SPI
EN
SOCHLR x 0 1 0 SOCH SOCL2 SOCL1 SOCL0
CDTOLR x 0 1 1 OL_dis CD_dis OCLT1 OCLT0
DICR x 1 0 0 FAST CSNS IN dis A/O
SR high
OSDR 0 1 0 1 0 OSD2 OSD1 OSD0
WDR 1 1 0 1 0
0
WD1 WD0
NAR 0 1 1 0 0
0
0
0
UOVR 1 1 1 0 0
0 UV_dis OV_dis
TEST x 1 1 1
Freescale Internal Use (Test)
x = Don’t care.
DEVICE REGISTER ADDRESSING
The following section describes the possible register
addresses and their impact on device operation.
Address x000 — Status Register (STATR)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D2, D1, and D0 determine the content of the first eight bits of
SO data. In addition to the device status, this feature provides
the ability to read the content of the OCR, SOCHLR,
CDTOLR, DICR, OSDR, WDR, NAR, and UOVR registers.
(Refer to the section entitled Serial Output Communication
(Device Status Return Data) beginning on page 24.)
Address x001 — Output Control Register (OCR)
The OCR register allows the MCU to control the output
through the SPI. Incoming message bit D0 (IN_SPI) reflects
the desired states of the high-side output: a Logic [1] enables
the output switch and a Logic [0] turns it OFF. A Logic [1] on
message bit D1 enables the Current Sense (CSNS) pin. Bits
D2 and D3 must be Logic [0]. Bit D7 is used to feed the
watchdog if enabled.
Address x010 — Select Overcurrent High and Low
Register (SOCHLR)
The SOCHLR register allows the MCU to configure the
output overcurrent low and high detection levels,
respectively. In addition to protecting the device, this slow
blow fuse emulation feature can be used to optimize the load
requirements to match system characteristics. Bits D2 : D0
are used to set the overcurrent low detection level to one of
eight possible levels as defined in Table 10. Bit D3 is used to
set the overcurrent high detection level to one of two levels
as defined in Table 11.
Table 10. Overcurrent Low Detection Levels
SOCL2 SOCL1 SOCL0
(D2)
(D1)
(D0)
Overcurrent Low Detection
(Amperes)
0
0
0
50
0
0
1
45
0
1
0
40
0
1
1
35
1
0
0
30
1
0
1
25
1
1
0
20
1
1
1
15
Table 11. Overcurrent High Detection Levels
SOCH (D3)
Overcurrent High Detection
(Amperes)
0
150
1
100
Address x011 — Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine
the amount of time the device will allow an overcurrent low
condition before output latches OFF occurs. Bits D1 and D0
allow the MCU to select one of four fault blanking times
defined in Table 12. Note that these timeouts apply only to
the overcurrent low detection levels. If the selected
overcurrent high level is reached, the device will latch off
within 20 µs.
Table 12. Overcurrent Low Detection Blanking Time
OCLT [1:0]
Timing
00
155 ms
01
10 ms
10
1.2 ms
11
150 µs
A Logic [1] on bit D2 disables the overcurrent low (CD_dis)
detection time-out feature. A Logic [1] on bit D3 disables the
open load (OL) detection feature.
Address x100 — Direct Input Control Register (DICR)
The DICR register is used by the MCU to enable, disable,
or configure the direct IN pin control of the output. A Logic [0]
on bit D1 will enable the output for direct control by the IN pin.
A Logic [1] on bit D1 will disable the output from direct control.
While addressing this register, if the input was enabled for
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Analog Integrated Circuit Device Data
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