908E626_09 Datasheet, PDF (21/44 Pages) Freescale Semiconductor, Inc – Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication

FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
RESET EXTERNAL SOURCE
External Reset Pin
The microcontroller has the capability of resetting the
SMARTMOS device by pulling down the RST pin.
Reset Mask Register (RMR)
Register Name and Address: RMR - $06
Bit7 6
5
4
3
2
1 Bit0
Read
0
0
0
0
0
TTEST
HVRE HTRE
Write
Reset 0
0
0
0
0
0
0
0
TTEST — High Temperature Reset Test
This read / write bit is for test purposes only. It decreases
the overtemperature shutdown limit for final test. Reset clears
the HTRE bit.
• 1 = Low temperature threshold enabled.
• 0 = Low temperature threshold disabled.
HVRE — High Voltage Reset Enable Bit
This read / write bit enables resets on high voltage
conditions. Reset clears the HVRE bit.
• 1 = High voltage reset enabled.
• 0 = High voltage reset disabled.
HTRE — High Temperature Reset Enable Bit
This read / write bit enables resets on high temperature
conditions. Reset clears the HTRE bit.
• 1 = High temperature reset enabled.
• 0 = High temperature reset disabled.
SERIAL PERIPHERAL INTERFACE
The serial peripheral interface (SPI) creates the
communication link between the microcontroller and the
908E626.
The interface consists of four pins (see Figure 11):
• SS—Slave Select
• MOSI—Master-Out Slave-In
• MISO—Master-In Slave-Out
• SPSCK—Serial Clock (maximum frequency 4.0 MHz)
A complete data transfer via the SPI consists of 2 bytes.
The master sends address and data, slave system status,
and data of the selected address.
SS
MOSI
Read/Write, Address, Parity
R/W A4 A3 A2 A1 A0 P X
Data (Register write)
D7 D6 D5 D4 D3 D2 D1 D0
MISO
System Status Register
S7 S6 S5 S4 S3 S2 S1 S0
Data (Register read)
D7 D6 D5 D4 D3 D2 D1 D0
SPSCK
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Figure 11. SPI Protocol
Slave latch
data
During the inactive phase of SS, the new data transfer is
prepared. The falling edge on the SS line indicates the start
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
The MISO output changes data on a rising edge of
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of SS.
Analog Integrated Circuit Device Data
Freescale Semiconductor
908E626
21