MC9S12DP512 Datasheet, PDF (2/124 Pages) Freescale Semiconductor, Inc – Microcontroller Unit (MCU)

Freescale Semiconductor, Inc.
DOCUMENT NUMBER
9S12DP512DGV1/D
Revision History
Version Revision Effective
Number Date
Date
V01.00
27 Nov
2001
11 Feb
2002
V01.01
13 Mar
2002
13 Mar
2002
V01.02
V01.03
V01.04
02 Apr
2002
15 Apr
2002
06 Jun
2002
02 Apr
2002
15 Apr
2002
06 Jun
2002
V01.05
05 Jul
2002
05 Jul
2002
Author
Description of Changes
- Initial version based on DP256 V2.09.
- Updated document formats.
- Removed reference to SIM in overview.
- Changed XCLKS to PE7 in signal description.
- Removed "Oscillator start-up time from POR or STOP" from Oscillator
Characterisitcs.
- Changed VDD and VDDPLL to 2.35V.
- Updated C_INS.
- Updated I_OL/I_OH values.
- Updated input capacitance.
- Updated NVM timing characteristics.
- Updated document reference (SPI, SCI).
- Corrected values in device memory map (RAM start, flash protected
sector sizes).
- Updated document reference (SCI).
- Changed all operating frequency references to 50MHz EXTAL and
removed references to 80 pin LQFP.
- Preface Table "Document References": Changed to full naming for
each block.
- Table "Interrupt Vector Locations", Column "Local Enable": Corrected
several register and bit names.
- Table "Signal Properties": Added column "Internal Pull Resistor".
- Table "PLL Characteristics": Updated parameters K1 and f1
- Figure "Basic Pll functional diagram": Inserted XFC pin in diagram
- Enhanced section "XFC Component Selection"
- Added to Sections ATD, ECT and PWM: freeze mode = active BDM
mode.
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