MC68882FN25A Datasheet, PDF (2/26 Pages) Freescale Semiconductor, Inc – HCMOS Enhanced Floating-Point Coprocessor

Freescale Semiconductor, Inc.
THE COPROCESSOR CONCEPT
HARDWARE OVERVIEW
The MC68882 functions as a coprocessor in systems
where the MC68020 or MC68030 is the main processor
via the M68000 coprocessor interface. It functions as a
peripheral processor in systems where the main proces-
sor is the MC68000, MC68008, or MC68010.
The MC68882 utilizes the M68000 Family coprocessor
interface to provide a logical extension of the MC68020
or MC68030 registers and instruction set in a manner
which is transparent to the programmer. The program-
mer perceives the MPU/FPCP execution model as if both
devices are implemented on one chip. A fundamental
The MC68882 is a high performance floating-point de-
vice designed to interface with the MC68020 or MC68030
as a coprocessor. This device fully supports the MC68020
or MC68030 virtual machine architecture and is imple-
mented in HCMOS, Motorola’s low power, small geom-
etry process. This process allows CMOS and HMOS (high
density NMOS) gates to be combined on the sa,,~<~~evice.
CMOS structures are used where speed a~@,l~~,~ower
is required, and HMOS structures are use~, W%re mini-
mum silicon area is desired. Using t~,~. ^{::W,t~.&.,W;.+ih.~o$l~ogy} in-
creases speed performance
whi~g%~!$..g,,.’~>low power
goal of the M68000 Family coprocessor interface is to
provide the programmer with an execution model based
upon sequential instruction execution by the MC68020
consumption, yet still
ably small die size.
confines _{,*,~t,hj,-,~.’.’J~‘!~~-~,I.$.~s‘.k\\,~\,.~“.~.;..~t+1~}
to _.a, reason-
The MC68882 can also Qf ~~,$as a peripheral pro-
or MC68030 and the MC68882. For optimum perform-
cessor in systems where t@@~~C68020 or MC68030 is not
ante, however, the coprocessor interface allows concur-
rent operations in the MC68882 with respect to the
MC68020 or MC68030 whenever possible. In order to sim-
plify the programmer’s model, the coprocessor interface
is designed to emulate, as closely as possible, non-con-
the main processor (e,&};,W&OOO, MC68008, MC68010).
The configuration o~$~ ,@68882 as a peripheral pro-
cessor or coprocqs$~@,..,s~,,‘’,m~#‘y be completely transparent to
user software (i.e.;%~~’%ame object code maybe executed
in either co~~$~::atfon).
current operation between the MC68020 or MC68030 and
The ar~&$,~~’re of the MC68882 appears to the user
the MC68882.
as a lo~i~.,1, e~tension of the M68000 Family architecture,
The MC68882 is a non-DMA type coprocessor which
Beca~$@o~the coupling of the coprocessor interface, the
uses a subset of the general purpose coprocessor inter-
~~fi80’* or MC68030 programmer can view the MC68882
face supported by the MC68020 or MC68030. Features of .,.~eg$~ters as though the registers are resident in the
the interface implemented in the MC68882 are as follows:
#“~68020
or MC68030. Thus, a MC68020 or MC68030 and
. The main processor(s) and MC68882 communicat~~~~‘jw’“$~e~ ^{MC68882 device pair functions as one processor with}
via standard M68000 bus cycles.
~.*!*>.~~ eight integer data registers, eight address registers, and
eight floating-point data registers supporting seven float-
. The main processor(s) and MC68882 cO.~mUti:i-
ing-point and integer data types.
cations are not dependent upon the a~@:a&cture
The MC68882 programming model is shown in Figures
of the individual devices (e.g., instruc@~$~ip&s or
caches, addressing modes).
V;>!]*Q,
, ^{~‘:)..:.+t*.fx{”,“i,.~.i.}
q The main processor(s) and MC6@~~~@ay operate
at different clock speeds.
,~“~:...,!?~.{..’,.xm:‘$,+,..:.<~’~\kl,
.?,$7:,*,,“’’”.:
1 through 6 and consists of the following:
q Eight 80-bit floating-point data registers (FPO-FP7).
These registers are analogous to the integer data
registers (DO-D7) and are completely general pur-
q MC68882 instructions util,i~~,a$~~ddressing modes
pose (i.e., any instruction can use any register).
provided by the main @#o<$#&or.
~:+~~’ \.;,~*,,*$
q All effective addreqqb~~q’y%calcu lated by the main
e _{A 32-bit control register that contains enable bits}
for each class of exception trap, and mode bits to
processor at th~t~~~si~ of the coprocessor.
set the user-selectable rounding and precision
q All data tran~fdxk$:~~e performed by the main pro-
modes.
cessor at ~~’~we~uest of the MC68882.
.*:\,ij+p,\:t
q Overla~@ ft’bncurrent) instruction execution en-
q A 32-bit status register that contains floating-point
condition codes, quotient bits, and exception sta-
han~,~~?~bughput
while maintaining the pro-
tus information.
g&~t@~*~r’s model of sequential
~f3%$BNiotn,
instruction
,,:,~’~~~~~dprocessor detection of exceptions which require
‘ ,J:g..t.,.....a _{trap to be taken are serviced by the main pro-}
8.~.:::.>.l’;.ti.$\~iJ,.,..>.,9_qtJ. ?Sc~eu.spspoorrt
at
the request of the MC68882.
of virtual memory/virtual machine
sys-
terns is provided via the FSAVE and FRESTORE
instructions.
q Up to eight coprocessor may reside in a system
simultaneously. Multiple coprocessor of the same
type are allowed.
q A 32-bit instruction address register that contains
the main processor memory address of the last
floating-point instruction that was executed. This
address is used in exception handling to locate the
instruction that caused the exception,
The connection between the MC68020 or MC68030 and
the MC68882 is a simple extension of the M68000 bus
interface. The MC68882 is connected as a coprocessor to
the MC68020 or MC68030, and the selection of the
MC68882 is based on a chip select which is decoded from
the MC68020 or MC68030 function codes and address
bus. Figure 7 illustrates the MPU/coprocessor configu-
. Systems may use software emulation of the
MC68882 without reassembling or relinking user
software.
ration.
As shown in Figure 8, the MC68882 is internally divided
into three processing elements: the bus interface unit
,p
p
\.;
..
,..-
,. -,
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MOTOROU
2
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