MC68882FN25A Datasheet, PDF(11/26 Page) Freescale Semiconductor, Inc – HCMOS Enhanced Floating-Point Coprocessor

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC68882FN25A Datasheet, PDF (11/26 Pages) Freescale Semiconductor, Inc – HCMOS Enhanced Floating-Point Coprocessor

◁

.. .

Freescale Semiconductor, Inc.

MISCELLANEOUS INSTRUCTIONS

unique format word prevents a saved MC68881 context

Miscellaneous instructions include moves to and from

the status, control, and instruction address registers, Also

included are the virtual memory/machine FSAVE and

FRESTORE instructions that save and restore the internal

state of the MC68882.

FMOVE

<ea>, FPcr Move to Control Register(s)

FMOVE

FSAVE

FPcr,<ea>

<es>

Move from Control Register(s)

Virtual Machine State Save

FRESTORE <es>

Virtual Machine State Restore

from being restored into an MC68882 and vice versa.

Second, the BSUN (Branch or Set on Unordered), SNAN

(Signaling Not-A-Number), OPERR (Operand Error), OVFL

(Overflow), DZ (Divide by Zero) and INEX (Inexact result)

floating-point exception handlers must have these min-

imum requirements:

1. An FSAVE must be executed before any other

floating-point instruction,

..~~~.j$

2, A BSET or sjmilar instruction that setsâ~~%1 of

the BI U flag word (located in the sa~~~J~T& state

frame),

<â.â..S:t:ik>tl,?.~.,.)..$(i:,,,$.â

ADDRESSING MODES

3. An FRESTORE instruction mus$~~i>kecuted be-

The MC68882 does not perform address calculations,

Thus, if the MC68882 instructs the MC68020 or MC68030

to transfer an operand via the coprocessor interface, the

MC68020 or MC68030 performs the addressing mode cal-

cubations requested in the instruction, In this case, the

instruction is encoded specifically for the MC68020 or

MC68030, and the execution of the MC68882 is depend-

ent only on the value of the command word written to

fore the RTE instruction.

~~,,o +tâ:s

,t>.?\â\:..<.~.*.1~!.,$:>.~!

The above requirements are ~&J<~p]icable to interrupt

handlers that do not conta~d~nyâ%oating-point

instruc-

tions. For interrupt hand~~~~wt have floating-point in-

structions,

implemented.

only req~,?.3~,M:g,.m*nts

~\~.$t~,\~..*+h.<. ,>..,,*,,

*;~!$$*â,&N,.,~\ :$?

~,:1i ,$,, â~$+:$

#1 and #3 must be

the MC68882 by the main processor.

This interface is flexible and allows any addressing

mode to be used with floating-point instructions, For the

M68000 Family, these addressing modes include im-

mediate, postincrement, predecrement, data or address

of the MC68020 and MC68030. Some addressing modes

,!sFâM.j!;..N?~,~~~,,1$>@,âc. ~

SIGNAL DESCRIPTIONS

The$~.UoWtng paragraphs contain a brief description

ofj~e iti~,ut and output signals for the MC68882 floating-

~~~~~,coprocessor. The signals are functionally organized

rYâ~fi@ groups as shown in Figure 10.

~k;%k:,,f~

are restricted for instructions consistent with the M6800&$Y;~$,:j

Family architectural definitions (e.g.; program counter ââik,

relative addressing is not allowed for a destination o~~

erand).

-> .,

,7{!.â*:,

:~:.,.~,s?

The orthogonal instruction set of the MC6~$&~$the

flexible branches and addressing modes o&~~~~r68020/

MC68030 allow a programmer or a cQ~p~&ââwriter to

think of the MC68882 as though it is,,~~$~fithe MC68020

or MC68030. There are no specia~ â~~t~$cllons imposed

by the coprocessor interface, ~~â~;~$j~ating-point arith-

NOTE

The terms assetiion and negation are used exten-

sively to avoid confusion when describing âactive-

lowâ and âactive-highâ signals. The term assert or

assertion is used to indicate that a signal is active

or true, independent of whether that level is rep-

resented by a high or low voltage. The term negate

or negation is used to indicate that a signal is in-

active or false.

metic

is coded

exactly like !,:i,n:,:,,tsâaâ.~,*$~:,,e*..i.~rd,ja.:r,~ith,\m. etic.

.,~~\,.t\$.p,~,\â,+â..::,.,*.1:1,â,*.,-*i,.$l+

MC6W8PQ6MPATIBILITY

,,~.>:$,::-,:.d..,~ââ+

Using the ~~~,~~~~n an existing MC68881 socket does

ADDRESS BUS (AO through A4)

These active-high address line inputs are used by the

main processor to select the coprocessor interface reg-

ister locations located in the CPU address space. These

lines control the register selection âas listed in Table 3.

not require&@~~*are changes nor user-software modi-

fications;<~J~@~entation

of multiple floating-point in-

structi@W ~~~cution concurrency gives the MC68882 a

âCc

GNO * 13

AO-A4

per~~â@&e advantage over the MC68881. However, to

g~.,~mtee that the floating-point exception model main-

~~~~~~the precepts of a sequential execution model, some

~~stems-level software modifications are needed to up-

grade the system to operate properly with an MC68882.

First, note that the idle and busy state frames (gener-

ated by the FSAVE instruction) are both 32 bytes larger

with the MC68882 than the MC68881, The offsets for the

exceptional operand, the operand register word, and the

BIU flag word from the top of the saved idle state frame

are 32 bytes more than that of the MC68881. However, a

DO-D31

MC6B882

FLOATING-POINT 4

COPROCESSOR

fl~

CLK

RESET

SENSE >

DSACKO

DSACK1 *

unique format word is generated by the MC68882 ens-

bling the system software to detect this difference. The

Figure 10. MC68882 Input/Output Signals

For More Information On This Product,

Go to: www.freescale.com

MC-

MOTOROLA

BRW/Rev. 3

,.,,, .7.. .,.,.,.,,,.......... ... .... . ..... ...... .,,.,,...,, . ......... . .. .. ..,, .,.,,. .. ........ . ., ..,,, ... .. . . ,,, ,,..

,, .,.

,,â

.. .. . ,,.

.. ..... . . .,,

.. . ......

..<

....

>.,..,,..

..............

,.,

....

.,,,.,â...,.,,.,,,,,,...,.,,,.,,.,.-..,.

.,.................;,..,.,,,

,. .;,

▷