MC68882FN25A Datasheet, PDF (10/26 Pages) Freescale Semiconductor, Inc – HCMOS Enhanced Floating-Point Coprocessor

Freescale Semiconductor, Inc.
The MC68882 monadic operations available are as fol-
the necessary condition checking and reports to the
lows:
MC68020 or MC68030 whether the condition is true or
FABS
Absolute Value
false. The MC68020 or MC68030 then takes the appro-
FACOS
Arc Cosine
priate action. Since the MC68882 and MC68020 or
FASIN
Arc Sine
MC68030 are closely coupled, the floating-point branch
FATAN
Arc Tanqent
operations execute very quickly.
FATANH
Hyperb&ic Arc Tangent
The MC68882 conditional operations are:
FCOS
Cosine
FBCC
Branch
FCOSH
Hyperbolic Cosine
FDBcc
Decrement and Branch,. ~$:<~
FETOX
e to the x Power
FSCC
Set According to CoQQi~~~S
FETOXMI
e to the X Power –1
FTRAPcc
Trap-on Condition ~’ $’! “
FGETEXP
FGETMAN
Get Exponent
Get Mantissa
where:
(with an Opti~”~l~~&?#meter)
,+*~,!~.,*.*/*Q.J:?!:,{.~&:,.
FINT
Integer Part
cc is one of the 32 floatind~@n$-~Onditional
test
FLINTRZ
FLOGIO
FLOG2
FLOGN
Integer Part (Truncated)
Log Base 10
Log Base 2
Log Base e
specifiers
as given in~%~~~@’
**1...*$..,f.y
\~:’’’:\i\%~:;:*h,~.;7\‘:.>.t,..,.,,<~..y,,}~,/..\,, ^~!?L.-
FLOGNPI
Log Base e of(x + 1)
Table 2. ,@~fi,~?-Point Conditional
FNEG
FSIN
FSINCOS
Negate
Sine
Simultaneous
Sine and Cosine
,e~;~~ Specifiers
‘._..._.._.,
~.:...>
Mnemo@$”~,,,:,,,
Definition
FSINH
FSQRT
Hyperbolic Sine
Square Root
,“$,.,,:,\’.\~$,$..‘:i.:-~.,~*\,.L\
\ ~.~,~,.,{.:a
NOTE
FTAN
Tangent
T@~$@lFB~lngconditional tests do not set the BSUN bit
FTANH
Hyperbolic Tangent
.%&int~g, status register exception byte under any circum-
FTENTOX
FTST
FTWOTOX
10 to the x Power
Test
2 to the x Power
DYADIC OPERATIONS
Dyadic operations have two operands
‘%$~tances.
&;if>:.,.i;h.):;.,’~.j<+F“
\$y[.::\k, ^{~ EQ}
>~...~.*‘:~>’ _OGT
~.+is ^..J,...,.,,,
~~,:’:~\.
OGE
OLT
OLE
e~$~$~’~~ first
OGL
False
Equal
Ordered Greater Than
Ordered Greater Than or Equal
Ordered Less ,Tha.n
Ordered Less Than or’ Equal
Ordered Greater or Less Than
operand is in a floating-point data regis\@Y, %?~orYt or
OR
Ordered
an MC68020 or MC68030 data registe~~’$:~~.:;~cond oP-
UN
Unordered
erand is the contents of a floating-p~~f$~~~% register. The
UEQ
Unordered or Equal
destination is the same floating-p~$~%.~%ta register used
UGT
Unordered or Greater Than
for the second operand.
ing-point add is:
For eix*..~,W&~,,l,~,th,e
syntax for float-
FADD.<fmt>
<~pP;&$
FADD.X
.~~,~~n
The dyadic oPeratiom$~/$@Table with the MC68882 are as
follows:
,Fi:}’~”h,..<,...:>. ^,:2$
FADD ~,.:,,..,,?‘ ^{,$l&~A d d}
FCMP,$Y2]Y, ‘;$r” Compare
FD,~~$;\;*
Divide
F~,@J>
i$y~~
Modulo Remainder
Multiply
ik~5Q$M
IEEE Remainder
*$~*FSCALE
?.\;*$,*\~.,T.,:;:,:.:,.,.<..:y,..*F,.SGLDIV
“\/.$, FSGLMUL
Scale Exponent
Single Precision Divide
Single Precision Multiply
FSUB
Subtract
UGE
ULT
ULE
NE
T
Unordered or Greater or Equal
Unordered or Less Than
Unordered or Less or Equal
Not Equal
True
NOTE
All the conditional tests below set the BSUN bit in the
status register exception byte if the NAN condition code
bit is set when a conditional instruction is executed.
SF
SEQ
GT
GE
LT
LE
GL
Signaling False
Signaling Equal
Greater Than
Greater Than or Equal
Less Than
Less Than or Equal
Greater or Less Than
GLE
Greater Less or Equal
BRANCH, SET, AND TRAP-ON CONDITION
NGLE
NGL
Not {Greater, Less or Equal)
Not (Greater or Less)
The floating-point branch, set, and trap-on condition
instructions implemented by the MC68882 are similar to
the equivalent integer instructions of the M68000 Family
processors, except more conditions exist due to the spe-
cial values in IEEE floating-point arithmetic. When a con-
ditional instruction is executed, the MC68882 performs
NLE
NLT
NGE
NGT
SNE
ST
Not (Less or Equal)
Not (Less Than)
Not (Greater or Equal)
Not (Greater Than)
Signaling Not Equal
Signaling True
$~::
r _Q;.>
MOTOROLA
10
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,,.
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