MC9S08SF4 Datasheet, PDF (18/32 Pages) Freescale Semiconductor, Inc – Technical Data

AC Characteristics
3.9.1 Control Timing
Table 9. Control Timing
Parameter
Symbol
Min
Typical¹
Max
Unit
Bus frequency (t_cyc = 1/f_Bus)
External reset pulse width²
IRQ pulse width
Asynchronous path²
Synchronous path³
KBIPx pulse width
Asynchronous path²
Synchronous path³
Port rise and fall time (load = 50 pF)⁴
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
f_Bus
1
—
t_extrst
100
—
t_ILIH, t_IHIL
100
1.5 t_cyc
—
t_ILIH, t_IHIL
100
1.5 t_cyc
—
t_Rise, t_Fall
—
3
—
30
20
MHz
—
ns
—
ns
—
ns
—
ns
—
BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
t_MSSU
500
—
—
ns
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes ⁵
t_MSH
100
—
—
μs
1 _{Data in Typical column was characterized at 5.0 V, 25 °C.}
2 _{This is the shortest pulse that is guaranteed to be recognized.}
3 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.}
5 _{To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD}
rises above V_LVD.
RESET PIN
t_extrst
Figure 14. Reset Timing
t_IHIL
IRQ/KBIPx
IRQ/KBIPx
t_ILIH
Figure 15. IRQ/KBIPx Timing
MC9S08SF4 Series MCU Data Sheet, Rev. 2
18
Freescale Semiconductor