LP1072 Datasheet, PDF (18/32 Pages) Freescale Semiconductor, Inc – 802.11a/b/g Baseband System Solution

Pinout and Footprint
Table 9. Pin Description (continued)
Pad Name
AVDD_PLL
AVSS_PLL
TAVDDPOWER
DVDD_PLL
DVSS_PLL
TXCO_BYPASS
TXCO_BYPASS_CLK
XTAL_BYPASS
XTAL_BYPASS_CLK
FAST_CLK_POWER
XTAL_32K_XIN
XTAL_32K_XOUT
RESET_N
CHIP_MODE0
CHIP_MODE1
CHIP_MODE2
CHIP_MODE3
JTAG
JTAG_RESET
JTAG_CLOCK
JTAG_DI
JTAG_DO
JTAG_MODE
ARM Sub-system Signals
ARM_GPIO0
ARM_GPIO1
ARM_GPIO2
ARM_GPIO3
ARM_GPIO4
ARM_GPIO5
ARM_GPIO6
ARM_GPIO7
ARM_UART_0_DI
ARM_UART_0_DO
ARM_EEPROM_DAT_GPIO
Pad Type
pdiana2p
pdiana2p
pvdd3p
pdiana2p
pdiana2p
pdidgz
pdidgz
pdidgz
pdidgz
pdo02cdg
pdxoe4dg
pdisdgz
pdidgz
pdidgz
pdidgz
pdidgz
pdudgz
pdisdgz
pdudgz
pdo02cdg
pdudgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
pdb04dgz
Direction
Description
Pin
N/A
N/A
N/A
N/A
N/A
Input
Input
Input
Input
Output
Analog
Analog
Input
Input
Input
Input
Input
Analog 1.8 volt
C1
Analog ground
D1
3.3 volt power for ESD Diodes
E3
1.8 volt digital power for PLL
E1
1.8 volt digital ground for PLL
E2
Bypass the TCXO and use the TCXO_BYPASS_CLK
C11
TCXO bypass clock
D11
Bypass XTAL osc and use XTAL_BYPASS_CLK
D15
XTAL bypass clock
D13
Enable the TCXO
C10
32kHz crystal (NOTE: Must be placed next to PVDD1DGZ.) C15
32kHz crystal
C14
Chip Reset
E13
Chip Mode Select
G2
0000 = SDIO normal operation
J1
0001 = CF+ normal operation
All other modes are reserved
H3
K1
Input Tap reset
P8
Input Tap clock
M8
Input Tap data in
R10
Output Tap data out
N10
Input Tap Mode
R11
Bi-dir General Purpose I/O
R1
Bi-dir General Purpose I/O
N3
Bi-dir General Purpose I/O
R3
Bi-dir General Purpose I/O
N4
Bi-dir General Purpose I/O
P4
Bi-dir General Purpose I/O
N5
Bi-dir General Purpose I/O
P5
Bi-dir General Purpose I/O
R5
Input UART input data
N7
Output UART output data
P6
Bi-dir General Purpose I/O dedicated for EEPROM
M7
LP1072 Advance Information, Rev. 0.3
18
Freescale Semiconductor
PRELIMINARY