LP1072 Datasheet, PDF (17/32 Pages) Freescale Semiconductor, Inc – 802.11a/b/g Baseband System Solution

6 Pinout and Footprint
Pinout and Footprint
6.1 Pinout
S
Table 9. Pin Description
Pad Name
Pad Type Direction
Description
Pin
Power and Ground Pads
VDD_IO
pvdd2dgz
N/A 3.3V I/O power pad (22 mA per pad max current)
K3
VDD_IO
pvdd2dgz
N/A 3.3V I/O power pad (22 mA per pad max current)
P3
VDD_IO
pvdd2dgz
N/A 3.3V I/O power pad (22 mA per pad max current)
M6
VDD_IO
pvdd2dgz
N/A 3.3V I/O power pad (22 mA per pad max current)
N11
VDD_IO
pvdd2dgz
N/A 3.3V I/O power pad (22 mA per pad max current)
R14
VDD_IO
pvdd2dgz
N/A 3.3V I/O power pad (22 mA per pad max current)
E12
VSS_IO
pvss2dgz
N/A I/O ground pad (94mA max current)
K5
VSS_IO
pvss2dgz
N/A I/O ground pad (94mA max current)
L5
VSS_IO
pvss2dgz
N/A I/O ground pad (94mA max current)
L6
VSS_IO
pvss2dgz
N/A I/O ground pad (94mA max current)
L8
VSS_IO
pvss2dgz
N/A I/O ground pad (94mA max current)
M11
VSS_IO
pvss2dgz
N/A I/O ground pad (94mA max current)
K11
VSS_IO
pvss2dgz
N/A I/O ground pad (94mA max current)
G11
VSS_IO
pvss2dgz
N/A I/O ground pad (94mA max current)
F11
VDD_CORE
pvdd1dgz
N/A 1.8V core power pad (31 mA per pad max current)
G1
VDD_CORE
pvdd1dgz
N/A 1.8V core power pad (31 mA per pad max current)
R8
VDD_CORE
pvdd1dgz
N/A 1.8V core power pad (31 mA per pad max current)
M10
VDD_CORE
pvdd1dgz
N/A 1.8V core power pad (31 mA per pad max current)
K15
VDD_CORE
pvdd1dgz
N/A 1.8V core power pad (31 mA per pad max current)
B15
VSS_CORE
pvss1dgz
N/A Core ground pad (25mA per pad max current)
H5
VSS_CORE
pvss1dgz
N/A Core ground pad (25mA per pad max current)
L7
VSS_CORE
pvss1dgz
N/A Core ground pad (25mA per pad max current)
L9
VSS_CORE
pvss1dgz
N/A Core ground pad (25mA per pad max current)
J11
VSS_CORE
pvss1dgz
N/A Core ground pad (25mA per pad max current)
E11
VSS_CORE
pvss1dgz
N/A Core ground pad (25mA per pad max current)
E9
Clocks and Resets and Mode
ARM_DBGEN
pdidgz
Input ARM7TDMI Icebreaker debug enable pin
F3
EMBEDDED_RESET_N
pdisdgz
Input Embedded board reset
F15
PLL_BYPASS
pdidgz
Input Bypass the internal PLL and use PLL_BYPASS_CLK
D10
PLL_BYPASS_CLK
pdidgz
Input PLL bypass clock input
A11
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
17
PRELIMINARY