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LP1072 Datasheet, PDF (12/32 Pages) Freescale Semiconductor, Inc – 802.11a/b/g Baseband System Solution | |||
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LP1072 Interfaces
Table 8. SDIO Function 1 Registers
Bit
Name
Description
ARM
Access
Watchdog Status Register (offset 0x000E)
0 Wdog_reset
This is a read only bit that when â1â indicates that
R
the LP1072 ASIC has had a watchdog reset
occur.
7:1 Reserved
â
â
SDIO Host to Device Interrupt request register 0 (0x000F)
7:0 Write_sdio_arm_int
Each bit in this register is 1 of 8 ARM interrupt
â
requests from the SDIO Host to the device ARM.
The Host should request an interrupt by writing a
â1â to the corresponding bit in this register. The
register will be read as a â1â until the ARM clears
the register. Once the ARM has cleared the
register then the corresponding bit will be read as
â0â again.
Device to SDIO Host Interrupt Source register 0 (0x0013)
7:0 Arm_to_sdio_int_clr[7:0] for This register contains the interrupt pending status
â
writes.
of the SDIO Host interrupt from the device. The
Arm_to_sdio_int_src[7:0] for device is capable of generating up to 8 individual
reads.
requests. Each bit in this register is ANDed with
the corresponding ARM to SDIO Host Interrupt
enable register. The ANDed bits are then ORed
together to generate a single SDIO Host interrupt
in the cccr register space. To clear a particular
interrupt bit the SDIO Host should write a â1â to
that particular bit in this register.
Device to SDIO Host Interrupt Source register 1 (0x0014)
2:0 Arm_to_sdio_int_clr[10:8] for This register contains the interrupt pending status -â¯
writes.
of the SDIO Host semaphore 0-2 host granted
Arm_to_sdio_int_src[10:8] indication. When the Host requests a semaphore
for reads.
the corresponding interrupt will be triggered when
the host has been granted the interrupt. Bit 0 is
semaphore 0; bit 1 is semaphore 1; and bit 2 is
semaphore 2. Each bit in this register is ANDed
with the corresponding ARM to SDIO Host
Interrupt enable register. The ANDed bits are then
ORed together to generate a single SDIO Host
interrupt in the cccr register space. To clear a
particular interrupt bit the SDIO Host should write
a â1â to that particular bit in this register.
7:3 Reserved
â
-â¯
HOST
Access
R
â
RW
RW
RW
-â¯
Reset
0
â
0âs
0âs
0âs
-â¯
LP1072 Advance Information, Rev. 0.3
12
Freescale Semiconductor
PRELIMINARY
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