FR015L3EZ Datasheet, PDF (8/12 Pages) Fairchild Semiconductor – Low-Side Reverse Bias / Reverse Polarity Protector

Application Test Configurations
Figure 15. Startup Test Circuit – No Reverse Polarity Protection
Typical Application Waveforms
─ V_IN, 2V/div. The input voltage between CTL and NEG
─ V_OUT, 2V/div. The output voltage between CTL and POS
─ V_D, 1V/div. The startup diode voltage between POS and NEG
─ i_IN, 5A/div. The input current flowing out of NEG
Time: 2µs/div
Figure 16. Normal Bias Startup Waveform, V_IN=3V, V₁=3V, C₁=5200µF, C₂=C₃=10µF, R₁=R₂=33kΩ, R₃=2Ω
© 2012 Fairchild Semiconductor Corporation
FR015L3EZ • Rev. A1
8
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