FR015L3EZ Datasheet, PDF (11/12 Pages) Fairchild Semiconductor – Low-Side Reverse Bias / Reverse Polarity Protector

Physical Dimensions
0.10 C
2.00
2X
A
B
1.00
6
(0.20)
4
No Traces allowed in
this Area
Pin #1 location
2.00
TOP VIEW
0.10 C
2X
1.05
(0.475)
1
0.65 TYP
1.35
2.30
3
0.40 TYP
RECOMMENDED LAND PATTERN OPT 1
0.8 MAX
0.10 C
0.08 C _00..0050
SEATING
PLANE
(0.20)
SIDE VIEW
C
PIN #1 IDENT
6X
0.33
0.20
0.50
1.00
0.80
1
0.15
0.50
0.30
3
0.61
0.51
1.05
0.95
6
4
0.65
1.30
0.35
0.25
6X
0.10
0.05
CAB
C
BOTTOM VIEW
1.00
6
0.45
0.20
4
1.05
0.661.352.30
1
0.65 TYP
3
0.40 TYP
RECOMMENDED LAND PATTERN OPT 2
A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION
MO-229 DATED AUG/2003
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. DRAWING FILENAME: MKT-MLP06Lrev3.
Figure 19. 6-Lead, Molded Leadless Package (MLP), Dual, Non-JEDEC, 2mm Square, Single-Tied DAP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/products/discrete/pdf/mlp2x2_tr.pdf
© 2012 Fairchild Semiconductor Corporation
FR015L3EZ • Rev. A1
11
www.fairchildsemi.com