FAN6520A_06 Datasheet, PDF (8/15 Pages) Fairchild Semiconductor – Single Synchronous Buck PWM Controller

Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the reference voltage level. The
error amplifier (Error Amp) output (V_E/A) is compared
with the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V_IN at the SW node. The PWM wave is smoothed by the
output LC filter (L_OUT and C_OUT).
OSC
PWM
V_IN
L_{OUT +VOUT}
SW
C_OUT
Q2
+5V
Z_FB
FB
COMP
Z_IN
ERROR
AMP
0.8V
DETAILED COMPENSATION
COMPONENTS
Z_FB C2
C1 _R2
Z_IN
C3 _R3
R1
COMP
FB
ERROR
AMP
0.8V
V_OUT
Figure 7. Voltage Mode Buck
Converter Compensation Design
The modulator transfer function is the small-signal trans-
fer function of V_OUT/V_COMP. This function is dominated
by a DC gain and the output filter (L_OUT and C_OUT), with
a double-pole break frequency at F_LC and a zero at
F_ESR. The DC gain of the modulator is the input voltage
(V_IN) divided by the peak-to-peak oscillator voltage
(ΔV_OSC. )
The following equations define the modulator break fre-
quencies as a function of the output LC filter:
F_LC
=
------------1------------
2π L × C
(3)
F_ESR
=
-----------------1-------------------
2π × ESR × C
(4)
The compensation network consists of the error amplifier
(internal to the FAN6520A) and the impedance networks
Z_IN and Z_FB. The goal of the compensation network is to
provide a closed-loop transfer function with the highest
0dB crossing frequency (F_0dB) and adequate phase mar-
gin. Phase margin is the difference between the closed-
loop phase at F_0dB and 180 degrees. The equations
below relate the compensation network’s poles, zeros,
and gain to the components (R1, R2, R3, C1, C2, and
C3), shown in Figure 7.
F_Z1
=
----------1-----------
2πR₂C₁
(5)
F_P1
=
-------------------1---------------------
2πR_{2⎝⎛ C----C-1}---¹-+--C---C--²---₂-_⎠⎞
(6)
F_Z2
=
-------------------1--------------------
2πC₃(R₁ + R₃)
(7)
F_P2
=
----------1-----------
2πR₃C₃
(8)
Use the following steps to locate the poles and zeros of
the compensation network:
1. Pick gain (R2/R1) for the desired converter band-
width.
2. Place the first zero below the filter’s double pole
(~75% F_LC).
3. Place the second zero at filter’s double pole.
4. Place the first pole at the ESR zero.
5. Place the second pole at half the switching fre-
quency.
6. Check the gain against the error amplifier’s open-
loop gain.
7. Estimate phase margin. Repeat if necessary.
Figure 8 shows an asymptotic plot of the DC-DC con-
verter’s gain vs. frequency. The actual modulator gain
has a high gain peak due to the high Q factor of the out-
put filter and is not shown in Figure 8. Using the above
guidelines should give a compensation gain similar to
the curve plotted. The open-loop error amplifier gain
bounds the compensation gain. Check the compensation
gain at FP2 with the capabilities of the error amplifier.
The closed-loop gain is constructed on the graph of Fig-
ure 8 by adding the modulator gain (in dB) to the com-
pensation gain (in dB). This is equivalent to multiplying
the modulator transfer function by the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance net-
works Z_FB and Z_IN to provide a stable high bandwidth
overall loop. A stable control loop has a gain crossing
with a –20dB/decade slope and a phase margin greater
than 45°. Include worst-case component variations when
determining phase margin.
©2005 Fairchild Semiconductor Corporation
FAN6520A Rev. 1.0.5
8
www.fairchildsemi.com